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Kris Gaj

Kris Gaj. Research and teaching interests: cryptography computer arithmetic VLSI design and testing Contact: Science & Technology II, room 223 kgaj@gmu.edu, kgaj01@yahoo.com, (703) 993-1575. Office hours: Monday, 7:30-8:30 PM

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Kris Gaj

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  1. Kris Gaj • Research and teaching interests: • cryptography • computer arithmetic • VLSI design and testing • Contact: • Science & Technology II, room 223 • kgaj@gmu.edu, kgaj01@yahoo.com, • (703) 993-1575 Office hours:Monday, 7:30-8:30 PM Thursday, 7:30-8:30 PM

  2. ECE 645 Part of: MS in CpE Digital Systems Design – required course Other concentration areas – elective course MS in EE Certificate in VLSI Design/Manufacturing PhD in ECE PhD in IT

  3. Spring 2006 Enrollment as of January 23, 2006 BS in CpE 1 NDG 1 PhD in IT 1 PhD in ECE 1 MS in CpE 7 MS in ISA 1 MS in EE 6

  4. DIGITAL SYSTEMS DESIGN • Concentration advisor: Ken Hintz • 1. ECE 545 Introduction to VHDL – K. Gaj, K. Hintz, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • 2. ECE 645 Computer Arithmetic: HW and SWImplementation – K. Gaj, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • 3. ECE 586 Digital Integrated Circuits – D. Ioannou • 4. ECE 681 VLSI Design Automation – T. Storey, project/lab, back-end design with Synopsys tools

  5. Courses Design level Computer Arithmetic VLSI Design Automation Introduction to VHDL algorithmic ECE 645 ECE 545 register-transfer ECE 681 gate ECE 586 transistor Digital Integrated Circuits layout Semiconductor Device Fundamentals MOS Device Electronics ECE 584 devices ECE684

  6. Prerequisites ECE 545 Introduction to VHDL or Permission of the instructor, granted assuming that you know VHDL orVerilog, High level programming language (preferably C)

  7. Course web page ECE web page  Courses  Course web pages  ECE 645 http://teal.gmu.edu/courses/ECE645/index.htm

  8. Computer Arithmetic Lecture Project Project 1 20 % Project 2 30 % Homework 15 % Midterm exam 1 (in class) 20 % Midterm exam 2(take-home) 15 %

  9. Advanced digital circuit design course covering Efficient • addition and subtraction • multiplication • division and modular reduction • exponentiation • Elements • of the Galois • field GF(2n) • polynomial base Integers unsigned and signed Real numbers • fixed point • single and double precision • floating point

  10. Lecture topics (1) INTRODUCTION 1. Applications of computer arithmetic algorithms 2. Number representation • Unsigned Integers • Signed Integers • Fixed-point real numbers • Floating-point real numbers • Elements of the Galois Field GF(2n)

  11. ADDITION AND SUBTRACTION 1. Basic addition, subtraction, and counting 2. Carry-lookahead, carry-select, and hybrid adders 3. Adders based on Parallel Prefix Networks

  12. MULTIOPERAND ADDITION 1. Carry-save adders 2. Wallace and Dadda Trees 3. Adding multiple signed numbers

  13. MULTIPLICATION 1. Tree and array multipliers 2. Sequential multipliers 3. Multiplication of signed numbers and squaring

  14. DIVISION • Basic restoring and non-restoring • sequential dividers • 2. SRTand high-radix dividers • 3. Array dividers

  15. FLOATING POINT AND GALOIS FIELD ARITHMETIC • Floating-point units • 2. Galois Field GF(2n) units

  16. Similar courses at other universities • University of California, Santa Barbara, Behrooz Parhami, • ECE252B: Computer Arithmetic. • University of Massachusetts, Amherst, Israel Koren, • ECE666: Digital Computer Arithmetic • Lehigh University, Michael Schulte, • ECE496: High-Speed Computer Arithmetic. • Worcester Polytechnic Institute, Berk Sunar, • EE-579 V Computer Arithmetic Circuits. • Stanford University, Michael Flynn, • EE486: Advanced Computer Arithmetic. • University of California, Davies, Vojin Oklobdzija, • ECE278: Computer Arithmetic for Digital Implementation.

  17. New in this course • real-life project based on VHDL or Verilog HDL • operations in the Galois Field • (with the application in cryptography • and communications)

  18. Possible topics for a Scholarly Paper or Research Project for the CpE & EE students Advanced Computer Arithmetic Square root Exponential and logarithmic functions Trigonometric functions Hyperbolic functions Fault-Tolerant Arithmetic Low-PowerArithmetic High-Throughput Arithmetic

  19. Three Curriculum Options 2 core courses 4 required courses 2 elective courses 3 elective courses 4 elective courses ECE 799 Master’s Thesis (6 cr. hrs) ECE 798 Research Project Scholarly paper Scholarly paper MS Thesis Option Research Project Option Scholarly Paper Option

  20. Literature (1) Required textbook: Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design, Oxford University Press, 2000. Recommended textbooks: Milos D. Ercegovac and Tomas Lang Digital Arithmetic, Morgan Kaufmann Publishers, 2004. Isreal Koren, Computer Arithmetic Algorithms, 2nd edition, A. K. Peters, Natick, MA, 2002.

  21. Literature (2) VHDL books (used in ECE 545 in Fall 2005) 1. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998. 2. Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004.

  22. Literature (3) Supplementary books: • E. E. Swartzlander, Jr., Computer Arithmetic, • vols. I and II, IEEE Computer Society Press, 1990. • 2. Alfred J. Menezes, Paul C. van Oorschot, • and Scott A. Vanstone, • Handbook of Applied Cryptology, • Chapter 14, Efficient Implementation, • CRC Press, Inc.,1998. • 3. Christof Paar, Efficient VLSI Architectures for Bit • Parallel Computation in Galois Fields, • VDI Verlag, 1994.

  23. Literature (3) Proceedings of conferences ARITH - International Symposium on Computer Arithmetic ASIL - Asilomar Conference on Signals, Systems, and Computers ICCD - International Conference on Computer Design CHES - Workshop on Cryptographic Hardware and Embedded Systems Journals and periodicals IEEE Transactions on Computers, in particular special issues on computer arithmetic: 8/70, 6/73, 7/77, 4/83, 8/90, 8/92, 8/94. IEEE Transactions on Circuits and Systems IEEE Transactions on Very Large Scale Integration IEE Proceedings: Computer and Digital Techniques Journal of VLSI Signal Processing

  24. Homework • reading assignments (main textbook + articles) • analysis of hardware and software algorithms • and implementations • design of small hardware units using VHDL or Verilog Optional assignments Possibility of trading analysis vs. design vs. coding

  25. Midterm exams Exam 1 - 2 hrs 30 minutes, in class multiple choice + short problems Exam 2 – 48 hrs, take-home analysis and design of arithmetic units using VHDL or Verilog HDL Practice exams on the web Tentative days of exams: Exam 1 - Monday, March 27 Exam 2 - Saturday-Sunday, May 6-7

  26. Project (1) Project I (20% of grade) Design and comparative analysis of fast adders (several hundred bits long) • Optimization criteria: • minimum latency • maximum throughput • minimum area • minimum product latency · area • maximum ratio throughput/area • scalability Similar for all students Done individually Final report due Monday, March 20

  27. Project (2) Project II (30% of grade) Long unsigned or signed integers • Fast • multiplication • squaring • division • modular reduction, or • modular exponentiation or Floating-point numbers • Fast • addition or • multiplication

  28. Project II (rules) • Real life application • Requirements derived from the analysis of the application • Typically both hardware and software design • Several project topics proposed on the web • You can choose project topic by yourself • Can be done in a group of 1-3 students Written report& oral presentation Monday, May 15

  29. Project II (rules) • Every team works on a slightly different problem • Project topics should be more complex for larger teams • Cooperation (but not exchange of code) • between teams is encouraged

  30. Project Hardware Software High level language (C preferred) VHDL (or Verilog) code Latency and/or throughput Execution time Area Memory requirements Scalability Scalability

  31. Degrees of freedom and possible trade-offs speed area ECE 645 power testability ECE 682 ECE 586, 681

  32. Degrees of freedom and possible trade-offs speed latency area throughput

  33. Timing parameters definition units pipelining time pointpoint ns delay ns bad latency time inputoutput throughput Mbits/s good #output bits/time unit rising edge rising edge of clock ns good clock period 1 MHz clock frequency good clock period

  34. Project technologies semi-custom Application Specific Integrated Circuits and Field Programmable Gate Arrays

  35. Levels of design description Algorithmic level Level of description most suitable for synthesis Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level

  36. Register Transfer Logic (RTL) Design Description Registers … Combinational Logic Combinational Logic Clock

  37. RTL Block Synthesis* Estimated Area Estimated Timing *Simplified design flow

  38. dataflow VHDL Design Styles VHDL Design Styles behavioral (algorithmic) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Test benches Subset most suitable for use in this course

  39. CAD software available at GMU (1) VHDL simulators • Aldec Active-HDL (under Windows) • available in the FPGA Lab, S&T II, room 203 • student edition can be purchased on an individual • basis ($59.95 + S&H) • ModelSim (under Unix) • available from all PCs in the ECE educational labs • using an X-terminal emulator • available remotely from home using a fast Internet • connection

  40. CAD software available at GMU (2) Tools used for logic synthesis FPGA synthesis • Synplicity Synplify Pro (under Windows) • Xilinx XST(under Windows) • available in the FPGA Lab, S&T II, room 203 ASIC synthesis • Synopsys Design Compiler (under Unix) • available from all PCs in the ECE educational labs • using an X-terminal emulator • available remotely from home using a fast Internet • connection

  41. CAD software available at GMU (3) Tools used for implementation (mapping, placing & routing) in the FPGA technology • Xilinx ISE (under Windows) • available in the FPGA Lab, S&T II, room 203

  42. How to learn VHDL for synthesis by yourself? • Lecture slides for ECE 545 from Fall 2005 • Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, • S & G Publishing, 1998. • Volnei A. Pedroni, Circuit Design with VHDL, • The MIT Press, 2004. • Individual or small-group hands-on sessions with the TA • Practice, Practice, Practice!!!

  43. Testbench Non-synthesizable testbench Synthesizable design entity . . . . Architecture N Architecture 2 Architecture 1

  44. Design Environment HDL Design (VHDL or Verilog) Actual Resultsvs. Expected ResultsComparison Test Vectors (Inputs) Reference Model ( C )

  45. Primary applications (1) Execution units of general purpose microprocessors Integer units Floating point units Integers (8, 16, 32, 64 bits) Real numbers (32, 64 bits)

  46. Primary applications (2) Digital signal and digital image processing e.g., digital filters Discrete Fourier Transform Discrete Hilbert Transform General purpose DSP processors Specialized circuits Real numbers (fixed-point or floating point)

  47. Primary applications (3) Coding Error detection codes Error correcting codes Elements of the Galois fields GF(2n) (4-64 bits)

  48. Secret-key (Symmetric) Cryptosystems key of Alice and Bob - KAB key of Alice and Bob - KAB Network Decryption Encryption Bob Alice

  49. Primary applications (4) Cryptography Secret key cryptography IDEA, RC6, Mars Twofish, Rijndael Elements of the Galois field GF(2n) (4, 8 bits) Integers (16, 32 bits)

  50. Main operations Auxiliary operations 2 x SQR32, 2 x ROL32 XOR, ADD/SUB32 RC6 MARS XOR, ADD/SUB32 MUL32, 2 x ROL32, S-box 9x32 XOR ADD32 Twofish 96 S-box 4x4, 24 MUL GF(28) Rijndael 16 S-box 8x8 24 MUL GF(28) XOR 8 x 32 S-box 4x4 Serpent XOR

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