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Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Designing Sequential Logic Circuits. November 2002. Sequential Logic. 2 storage mechanisms. • positive feedback. • charge-based. Naming Conventions. In our text:

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing SequentialLogic Circuits November 2002

  2. Sequential Logic 2 storage mechanisms • positive feedback • charge-based

  3. Naming Conventions • In our text: • a latch is level sensitive • a register is edge-triggered • There are many different naming conventions • For instance, many books call edge-triggered elements flip-flops • This leads to confusion however

  4. Latch versus Register • Latch stores data when clock is low • Register stores data when clock rises D Q D Q Clk Clk Clk Clk D D Q Q

  5. Latches

  6. Latch-Based Design • N latch is transparentwhen f = 0 • P latch is transparent when f = 1 f N P Logic Latch Latch Logic In synchronous sequential circuits the next cycle cannot begin unless all current computations have completed and system has come to rest. The clock period T, at which the sequential ckt., operates, must thus accommodate the longest delay of any stage in the network.

  7. Timing Definitions CLK t t t su hold Register D DATA STABLE D Q t t c q 2 CLK Q DATA STABLE t

  8. Maximum Clock Frequency Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay tclk-Q + tp,comb + tsetup = T

  9. Static versus Dynamic Memory • Feedback loop stores data till power is supplied • Data stored on capacitor (needs refreshing)

  10. V Vi2 V V i o1 1 o 2 A C B V V = = V V i i 1 2 o o 2 1 Positive Feedback: Bi-Stability

  11. Meta-Stability Gain should be larger than 1 in the transition region

  12. CLK D D CLK Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state (can implement as NMOS-only) Converting into a MUX

  13. Q 0 Q 1 D 1 D 0 CLK Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK

  14. Mux-Based Latch clock load of 4 transistors

  15. Mux-Based Latch Noise margin issue nMOS pass Vdd -Vtn D NMOS only Non-overlapping clocks

  16. Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

  17. Master-Slave Register Multiplexer-based latch pair using TG (smaller clock load) setup time = (through I1, T1, I3 and I2) tc-q=tpd_tx +tpd_inv (through T3 and I6)

  18. Clk-Q Delay simulation of propagation delay of Transmission Gate register

  19. Reduced Clock Load Master-Slave Register • Feedback transmission gate can be eliminated by directly cross coupling the inverters • Reverse conduction possible in the transmission gate • As long as I4 is a weak device this is not a problem

  20. Avoiding Clock Overlap (clock skew) X CLK CLK Q A D B if there is clock overlap between CLK and CLK’ node A can be driven by both D and B, resulting in an undefined state CLK CLK (a) Schematic diagram CLK CLK (b) Overlapping clock pairs

  21. Overpowering the Feedback Loop ─Cross-Coupled Pairs (static) NOR-based set-reset

  22. Cross-Coupled NAND Added clock Cross-coupled NANDs This is not used in datapaths any more,but is a basic building memory cell CMOS clocked SR flip-flop

  23. Sizing Issues Output voltage dependence on transistor width Transient response

  24. Storage Mechanisms Dynamic (charge-based) Static C consisting of gate cap of Inv and junction cap of TG • setup time is simply the delay of T1 • hold time is zero since T1 turns OFF on next clock edge and further i/p changes are ignored • tc-q is equal to two inverter delays plus delay of T2

  25. Making a Dynamic Latch Pseudo-Static Slight cost in delay, it improves the noise immunity

  26. Other Latches/Registers: C2MOS “Keepers” can be added to make circuit pseudo-static

  27. Insensitive to Clock-Overlap V V V V DD DD DD DD M M M M 2 6 2 6 D M M 0 0 4 8 X X Q D Q M M 1 1 3 7 M M M M 1 5 1 5 (a) (0-0) overlap (b) (1-1) overlap

  28. Pipelining Resource utilization Pipelined Reference

  29. Other Latches/Registers: TSPC True Single Phase Clocked - register Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0)

  30. Including Logic in TSPC Example: logic inside the latch AND latch

  31. TSPC Register

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