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PCI Express* 2.0 Platform Implementations

PCI Express* 2.0 Platform Implementations. Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup. Today’s Topics. PCIe* Architecture Overview PCIe 2.0 Update Future of PCIe Architecture Call to Action. Signaling bump to 5G FLR, completion TO, etc.

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PCI Express* 2.0 Platform Implementations

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  1. PCI Express* 2.0Platform Implementations Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

  2. Today’s Topics • PCIe* Architecture Overview • PCIe 2.0 Update • Future of PCIe Architecture • Call to Action

  3. Signaling bump to 5G FLR, completion TO, etc Address Translation Services (ATS) Device sharing for Single/Multi-Root (SR/MR) Performance/power-optimized interface to host Protocol and SW extensions PCIe Architecture Overview New Extensions IOV PCIe 2.0 Today’s Focus

  4. PCIe 2.0 Update • 5GT/s Speed Increase • Link Speed Management • Link Bandwidth Notification Mechanism • Function Level Reset (FLR) • Access Control Services (ACS) • Completion Timeout Control • Retracted: Trusted Configuration Space (TCS)

  5. Reference Clock 100MHz Tx pins Rx pins PLL PLL Receiver Transmitter Channel Coupling caps PCIe 2.0 (5G) • Tight budgets remove all guard bands! • All interconnect components specified for enhanced interoperability • PCIe 1.0a: Transmitter • PCIe 1.1: PCIe 1.0a + Reference Clock • PCIe 2.0: PCIe 1.1 + Channel + Receiver • CEM specification provides electrical interoperability for system board/add-in card

  6. PCIe 2.0 LTSSM Extensions

  7. Link Speed Management • Default: Trains to the greatest common speed • Software can set an upper bound on the speed • Hardware can limit speed for link reliability • Hardware is permitted to change the speed autonomously • E.g.: Power management • Software can disable • New mechanism supporting software control for entering/exiting Compliance Mode

  8. Link Capability register Maximum Link Speed field renamed to Supported Link Speeds Link Status register Link Speed field renamed to Current Link Speed (New) Link Control 2 register Hardware Autonomous Speed Disable bit Enter Compliance bit Target Link Speed field Link Speed Controls

  9. Bandwidth Notification • Mechanism for PCIe-aware software to be notified when link bandwidth changes • E.g.: Link retrains to a lower bandwidth due to reliability problem • E.g.: Hardware-autonomous link retraining • Logically coupled with Link Speed Management • Required for all Root Ports and downstream Switch Ports that support wider than x1 and/or multiple link speeds

  10. Link Capability register Link Bandwidth Notification Capability bit Link Control register Link Autonomous Bandwidth Interrupt Enable bit Link Bandwidth Management Interrupt Enable bit Hardware Autonomous Width Disable bit Link Status register Link Autonomous Bandwidth Status bit Link Bandwidth Management Status bit BW Notification Mechanism

  11. Function Level Reset • New type of reset • Existing resets may (but not required to) reset function internals • FLR definition requires function internal reset • SW initiated function-specific reset RESET “FAMILY TREE” Conventional FLR Cold / Warm (PERST#) Hot S.B.R.

  12. FLR F0 F1 F2 PCIe EPs FLR Details • Endpoints only • All types: Legacy, native, integrated • Register interface simple • Implementation and effects potentially complex • Resets internal function-specific state • Not all architected registers are reset • Hardware initialized (HwInit), BIOS set, etc

  13. Access Control Services • For downstream ports and multi-function devices • New Extended Capability and Status/Mask/Severity bits in AER • Source validation • Downstream ports range check Requester ID BusNum in upstream Request TLPs • Peer-to-peer controls • Determine whether to forward directly, block, or redirect peer-to-peer requests to the RC for access validation • ACS considered for functionality defined by the Address Translation Services (ATS) specification

  14. 4s to 64s 250ms to 4s 10ms to 250ms 50us to 10ms Completion Timeout • Required: Architected Disable Bit • “Turns off” timeout • Not to be used in normal operation • Optional: Completion Timeout Programmability • Devices indicate supported ranges from the four bins defined • Two selectable ranges for each bin

  15. Future Of PCI Express Architecture

  16. Factors Driving PCIe Future • Multi-Everything! • CPUs, multi-core, operating systems • Device virtualization and sharing • Multiple graphics cards • Higher Performance • Next generation graphics, storage, networking, and fabrics • Emerging applications: Math, visualization, content processing, etc • Need for more connectivity: Flexible interconnect width/speed • Lower power • Technology Advances • Si process • High volume manufacturing • Materials PCIe is the interconnect of choice

  17. General IO Visualization Math Content Proc. Communication Applications SW Apps OS+LIB/APIs OS Synch. and Data Exchange Device Driver Device I/F OS Bus Driver, Cfg, PM, RAS PCI SW Model BW, Latency and Efficiency Protocol Power State Management Link PCIe Physical Signaling Speed Upgrade PCIe Architecture Evolution

  18. Call To Action • Innovate and differentiate your products with PCI Express 2.0 industry specification • Contribute to the evolution of PCI Express architecture • Visit www.pcisig.com for PCI Express specification updates

  19. Additional Resources • Web Resources: www.pcisig.com • Related Sessions • SYS-T311 – PCI I/O Virtualization Standards – Implementation

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