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EFFICIENT ERROR-CANCELLING ALGORITHMIC ADC

EFFICIENT ERROR-CANCELLING ALGORITHMIC ADC. Adviser: Dr.Hsun-hsiang Chen Presenter : Chieh-En Lo. OUTLINE. Introduction Converter structure Accurate residue amplification Simulation results. INTRODUCTION. medium-speed high-resolution

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EFFICIENT ERROR-CANCELLING ALGORITHMIC ADC

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  1. EFFICIENT ERROR-CANCELLING ALGORITHMIC ADC Adviser: Dr.Hsun-hsiang Chen Presenter : Chieh-En Lo

  2. OUTLINE • Introduction • Converter structure • Accurate residue amplification • Simulation results

  3. INTRODUCTION • medium-speed high-resolution • Most recent technique that uses a minimum of 7 clock periods per bit conversion, all tasks in the new technique is accomplished in 4 clock periodsper bit. • The key concept is to manipulate the switching of capacitors.

  4. CONVERTER STRUCTURE V(k+1) = 2V(k)+b(k)Vref

  5. ACCURATE RESIDUE AMPLIFICATION(1/3)

  6. Accurate residue amplification(2/3)

  7. Accurate residue amplification(3/3)

  8. SIMULATION RESULTS

  9. SNDR can be improved from 57db to 90db. • The proposed ADC is being designed and fabricated to achieve 1.8 V, 100 ksample/s and 16 bit resolution with 0.18 pm double-poly CMOS process. The expected active area is about 600 um x 700um, and the expected power consumption is about 4 mW

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