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ITRS 2002 Kickoff Update – ORTC Model Review

ITRS 2002 Kickoff Update – ORTC Model Review. IRC/ITWG Plenary 4/16/2002 Alan Allan Rev 0 - 4/15/2002. Some Key Challenges. “Red Brick Wall Shifts” 1999 vs 2001 ORTC Scaling Goals Device Scaling Challenges. The “ Red Brick Wall ” - 2001 ITRS vs 1999.

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ITRS 2002 Kickoff Update – ORTC Model Review

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  1. ITRS 2002 Kickoff Update – ORTC Model Review IRC/ITWG Plenary 4/16/2002 Alan Allan Rev 0 - 4/15/2002 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  2. Some Key Challenges • “Red Brick Wall Shifts” 1999 vs 2001 • ORTC Scaling Goals • Device Scaling Challenges 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  3. The “Red Brick Wall” - 2001 ITRS vs 1999 Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  4. Roadmap Acceleration and Deceleration 2001 versus 1999 Results Year of Production: 1999 2002 2005 2008 2011 2014 DRAM Half-Pitch [nm]:180 130100 70 50 35 Overlay Accuracy [nm]: 65 45 3525 20 15 MPU Gate Length [nm]: 14085-90 65 45 30-32 20-22 CD Control [nm]:1496 4 3 2 TOX (equivalent) [nm]: 1.9-2.51.5-1.91.0-1.5 0.8-1.2 0.6-0.8 0.5-0.6 Junction Depth [nm]: 42-70 25-4320-3316-26 11-19 8-13 Metal Cladding [nm]: 17 13 10 000 Inter-Metal Dielectric K: 3.5-4.0 2.7-3.5 1.6-2.2 1.5 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  5. 2001 ITRSSCALING Timing Highlights • The DRAM Half-Pitch (HP) remains on a 3-year-cycle trend after 130nm/2001 • The MPU/ASIC HP remains on a 2-year-cycle trend until 90nm/2004, and then remains equal to DRAM HP (3-year cycle) • The MPU Printed Gate Length (Pr GL ) and Physical Gate Length (Ph GL) will be on a 2-year-cycle until 45nm and 32nm, respectively, until the year 2005 • The MPU Pr GL and Ph GL will proceed parallel to the DRAM/MPU HP trends on a 3-year cycle beyond the year 2005 • The ASIC/Low Power Pr/Ph GL is delayed 2 years behind MPU Pr/Ph GL • ASIC HP equal to MPU HP 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  6. 1994 NTRS - .7x/3yrs Log Half-Pitch Actual - .7x/2yrs 0.7x 0.7x Linear Time 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% 0.5x N N+1 N+2 * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Source: 2001 ITRS - Exec. Summary Scaling Calculator + Node Cycle Time: 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  7. Production Ramp-up Model and Technology Node 100M 200K Development Production 10M 20K 1M 2K Volume (Parts/Month) Alpha Tool Beta Tool Production Tool 100K Volume (Wafers/Month) 200 10K First Two Companies Reaching Production 20 First Conf. Papers 1K 2 0 12 24 -24 -12 Months Source: 2001 ITRS - Exec. Summary 7 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  8. 10 10 For 1995-1999 W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value) W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. W.P.C. >0.7 mm 0.4-0.7 mm <0.4mm Sources: 1995 to 1999: SICAS 2000: Yano Research Institute& SIRIJ 1 1 For 2000 Feature Size of Technology Feature Size (Half Pitch) (mm) >0.8 mm 0.5-0.8 mm 0.35-0.5 mm 0.25- 0.35 mm 0.2 - 0.25 mm 0.18 - 0.2 mm <0.18 mm 0.1 0.1 ITRS Technology Node 0.01 0.01 1995 1995 2005 2005 1996 1996 1997 1997 1998 1998 1999 1999 2000 2000 2001 2001 2002 2002 2003 2003 2004 2004 Year Year Source: 2001 ITRS - Exec. Summary Technology Node vs Actual Wafer Production Capacity 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  9. [3-Year Node Cycle] [Node = DRAM Half-Pitch (HP)] [MPU Gate Length Cycle (GL)]: [2-year cycle] [3-year cycle] [MPU HP/GL Cycle]: [3-year cycle] 2001 ITRS ORTC Node Tables – w/Node Cycles 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  10. Source: 2001 ITRS - Exec. Summary, ORTC 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  11. DRAM Cell Area History / 2001 ITRS Model Historical Actual <- > 2001 ITRS Sources: Sematech, 2001 ITRS ORTC 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  12. (Cell Array Area / Chip Size) x 100 = Cell Array Efficiency (%): Chip Size = (A x f 2 x Nbits)/CAE Cell Array Area = Cell Area x number of bits (2 n) f 2 Cell Area = Cell Area Factor (A) x f 2 ; f = technology node (half-pitch) feature size; Example: Cell Area = 2x4 x f 2 = 8 f 2 Chip Size Model Calculation Illustration - DRAM 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  13. DRAM Cell Area History / 2001 ITRS Model DRAM Cell Area Historical Actual <- > 2001 ITRS History <-- 2000 --> F'cast 10 1 Mb 0.35x / 3 Years –29%/yr Actual Scaling Acceleration, Or Equivalent Scaling InnovationNeeded to maintain historical trend (est.) CAF (A) = 31 = 31/1.0^2 29 (per 1 FEP) 4 Mb 16 Mb CAF (A) CAF (A) 64 Mb = 22 = = 16 = CAF (A) 11/.71^2 4.0/.5^2 = 11 = 26 (per 21 (per 1.3/.35^2; FEP) FEP) .71/.25^2 Cell Area (u2) 0.1 16->10 (per FEP) 128/256Mb 512Mb CAF (A) = 8.0 = DRAM Cell Size Historical Trend: Half-Pitch Scaling, contributed ~ .5x / 3 years [(.7x)^2] Cell Design innovation contributed additional ~ .7x / 3 years .35/.21^2; .26/.18^2 1Gb / 2Gb 10 -> 8 (per FEP) CAF (A) = 6 0.01 4Gb / 8Gb CAF (A) = 6 16Gb / 32Gb CAF (A) = 4 0.001 1986 1989 1992 1995 1998 2001 2004 2007 2010 2013 2016 64 Gb/128Gb Sources: Sematech, 2001 ITRS ORTC Year CAF (A) = 4 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  14. Source: 2001 ITRS - Exec. Summary, ORTC 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  15. Table 4c Performance and Package Ch ips: Frequency On - Chip Wiring Levels — Near - Term Years 2001 2002 2003 2004 2005 2006 2007 Y P EAR OF RODUCTION 130 115 100 90 80 70 65 DRAM ½ Pitch (nm) 150 130 107 90 80 70 65 MPU/ASIC ½ Pitch (nm) 90 75 65 53 45 40 35 MPU Printed Gate Length (nm) Chip Frequency (MHz) 65 53 45 37 32 28 25 MPU Physical Gate Length (nm) 1,684 2,317 3,088 3,990 5,173 5,631 6,739 On chip local clock - Chip - to - board (off - chip) speed 1,684 2,317 3,088 3,990 5,173 5,631 6,739 (high - performance, for peripheral buses)[1] 7 8 8 8 9 9 9 Max imum number wiring levels — maximum 7 7 8 8 Maximum number wiring levels — minimum 8 9 9 [2-Yr GL Cycle; then 3-Yr] Table 4d Performance and Package Chips: Frequency, On - Chip Wiring Levels — Long - term Years 2010 2013 2016 Y P EAR OF RODUCTION 45 32 22 DRAM ½ Pitch ( nm) 45 32 22 MPU/ASIC ½ Pitch (nm) 25 18 13 MPU Printed Gate Length (nm) 18 13 9 MPU Physical Gate Length (nm) Sources: 2001 ITRS ORTC Chip Frequency (MHz) 11,511 19,348 28,751 On chip local clock - Chip - to - board (off - chip) speed 11,511 19,348 28,751 (high - performance, for peripheral buses)[1] 10 10 10 Maximum number wiring levels — maximum [3-year cycle] 9 9 10 Maximum number wiring levels — minimum 2001 ITRS ORTC MPU Frequency Tables – w/Node Cycles 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  16. MPU Clock Frequency Actual vs ITRS Historical <- > 1999 ITRS 2001 ITRS 100,000 2X / 4 Years 10,000 Actual Scaling Acceleration, Or Equivalent Scaling InnovationNeeded to maintain historical trend 1,000 Frequency (MHz) 2X / 2½ Years 100 MPU Clock Frequency Historical Trend: Gate Scaling, Transistor Design contributed ~ 17-19%/year Architectural Design innovation contributed additional ~ 21-13%/year 2X / 2 - 2½ Years 10 1 1980 1985 1990 1995 2000 2005 2010 2015 16 Sources: Sematech, 2001 ITRS ORTC

  17. Summary • Technology acceleration continued with 2001 ITRS • DRAM half-pitch is expected to return to a 3-year cycle after 2001 but….so we have said before • The Red Brick Wall is still there but it has become permeable • Innovation will be necessary, in addition to technology acceleration, to maintain historical performance trends 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  18. Summary(cont.) • Major challenges have been identified by each of the ITWGs – many opportunities for innovative R&D • Many material transitions are needed, but not sufficient, in the next few years to maintain the scaling pace • Close coordination of design, process integration and packaging is required to meet system requirements in the future • ITRS online resources at:http://www.sematech.org/public/resources/index.htm 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  19. ITRS 2003 2-year Update Proposal IRC 4/16/2002 Alan Allan Rev 0 - 4/10/2002 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  20. 2003 ITRS Renewal Proposal (04/16/02): 2-year Node Cycle • the DRAM Half-pitch (HP) continues on a 2-year-node-cycle trend after 130nm/2001 at least through 2011, or until “RED” (no Known Solutions), then return to 3-year-node-cycle • the MPU/ASIC HP* will be on a 2-year-cycle trend until 90nm/2004, and then continue parallel to DRAM HP, but 1-year behind DRAM • the MPU (HP) Printed (PrGL) and Physical (PhGL) Gate Length will be on 2-year-cycle trends until 45nm and 32nm, respectively, at year 2005, and then remain parallel to the DRAM/MPU HP trends on a 2-year cycle, or until “RED” (no Known Solutions), then 3-yr cycle • the ASIC/Low Power Pr/PhGL is delayed 2 years behind MPU Pr/PhGL; *ASIC/Low Power HP equal to MPU HP • ITWG Table Columns may not track their respective Node Headers, depending on TWG model algorithm relationship to the technology node (example DRAM capacitor, MPU power, frequency) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  21. [3-Year Node Cycle] [Node = DRAM Half-Pitch (HP)] [MPU Gate Length Cycle (GL)]: [2-year cycle] [3-year cycle] [MPU HP/GL Cycle]: [3-year cycle] 2001 ITRS ORTC Node Tables – w/Node Cycles 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  22. 2003 Renewal 2-yr (through 2011) Node Proposal – ITRS ORTC Annualized Node Tables (3-yr cycle after 2011) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  23. (2-yr cycle extended) 2-year Cycle DRAM H.Pitch ? ? 2-year Cycle MPU/ASIC H.Pitch (1-yr delay) ? 3-year Cycle 2002 Update Proposal: 2-yr Node Cycle through 2011 (presently through 2001 for Half-Pitch) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  24. (2-yr cycle extended) 2-year Cycle MPU Physical GL (50% of DRAM H.pitch) 2-year Cycle MPU Printed GL (70% of DRAM H.pitch) ? ? 3-year Cycle ? 2002 Update Proposal: 2-yr Node Cycle through 2011 (presently through 2005 for Gate Length) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  25. Historical Node Cycle ITRS Trend Analysis 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  26. Recent Company Announcements ITRS Trend Analysis 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  27. Proposed 2-Year Cycle DRAM Model Assumptions • 2-YEAR NODE CYCLE 2011, then return to 3-year cycle • Cell Area Factor (CAF=A) (design/process improvement) targets are as follows: 1999–2002/ 8; 2003–2010/ 6; 2011–2016/ 4 (no change from 2001 ITRS) • DRAM product generations are increased by 4x bits/chip every four years with interim 2x bits/chip generations - NO SLOWING THE RATE OF BITS/CHIP TO 4X/5-6YRS IS REQUIRED • InTER-generation chip size growth rate varies to maintain one chip per 572mm2 field at Introduction(SOMETIMES 2/FIELD) and FOUR TO FIVE chips per 572mm2 field atProduction. • The InTRA-generation chip size shrink model is 0.5x every technology node (2 YEARS) in-between cell factor reductions. • Cell Array Efficiency (CAE) improves only slightly (less than 1% per year - no change from 2001 ITRS) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  28. 3-yr Node Cycle vs 2-yr 0.89/yr 0.95/yr 0.71/yr 0.74/yr 3-Year 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  29. 3-yr Node Cycle vs 2-yr 0.89/yr 0.95/yr 0.71/yr 2-Year 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  30. 1.26/yr 1.41/yr 0.71/yr 1.59/yr 0.74/yr 3-Year 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  31. 1.41/yr 0.71/yr 1.59/yr 2-Year 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  32. MPU Chip size - 2000 ITRS ORTC Update Proposal [ Sc. 2.0 vs 3.7 vsDesign TWG 2001 ITRS * vs 2-yr Node Proposal ] 800mm2 Litho Field Size 572mm2 Litho Field Size 286mm2 2 per Field Size 310mm2 340mm2 HP MPU 310mm2 1999 Typical .18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2 170mm2 CP MPU 140mm2 Sc 3.7: Flat Thru 2004 85mm2 1999 Typical .18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 42mm2 * Design TWG MPU Transistors/Chip Proposal: ~2x/Node = 2x/2yrs from 1999-2001; then 2x/3yrs from 2001-2016 2-year Cycle => 2x Tr/chip/2yrs 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  33. Chip Function Area (1/Density) Trend Chart 137f2 x1.6 2001 ITRS: [A x f^2 x 1/CAE] Design TWG MPU Chip: Ave. Size/Function Density Model: Constant Chip Size Target ; Density Increases 2x / node MPU 2-yr: Litho .84^2 x Design 1.0 = .71x/yr = -29%/yr 97f2 x1.6 3/12/02 CeBit – Intel: 90nm, 1u2 cell, 52Mb, 330Mt, 109mm2 (2u2 cell ave), SRAM, Af2/CAE=123*.09^2*2 2003 production MPU 3-yr: Litho .89^2 x Design 1.0 = .79x/yr = -21%/yr 320f2 x2 320f2 x2 SRAM 2-yr: Litho .84^2 x Design 0.98x = .69x/yr = -31%/yr 320f2 x2 137f2 x1.6 123f2 x2 23f2 x1.6 20f2 X2 320f2 x2 2-yr to 2011, then 3-yr : 97f2 x1.6 4t Gate -26% CADR 13f2 x1.6 6t Cell = ASIC Gate (4t) , eSRAM (6t) (Design TWG) Transistor SRAM 3-yr: Litho .89^2 x Design 0.98x = .78x/yr = -22%/yr 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  34. Summary • Proposal for 2003 ITRS to 2-year Node Cycle through 2011, or until “Red Limit” is encountered • Annual Data Columns will be required to track 2-year acceleration pull-in from the years beyond 2007 • 2-year Cycle through 2011 for DRAMs will: • put DRAM Cell Size trend back on historical rate • avoid additional slowing of bits/chip • allow flat chip size and 4/chips per 572mm2 “affordable” litho field at Production • However, FEP must evaluate potential “RED” limitation of capacitor storage and high-K material – may become the size limiter – not half-pitch 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  35. Summary (cont.) • 2-year Cycle through 2011 for MPUs (chip size and density model tied to Node timing) will: • Contribute to returning the MPU Frequency trend back on historical rate (but Architecture Design needed) • put MPU SRAM and Logic Density trend back on historical rate • avoid additional slowing of transistors/chip • continue flat chip size (140mm2) and 4/chips per 572mm2 “affordable” litho field at Production • However, FEP, PIDs, Design, and A&P must evaluate potential “RED” limitation of Power Dissipation and Frequency tradeoffs – may become limiter – not gate length (algor’s needed) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  36. Back up 2002 ITRS Update Proposal – Work in Progress – Do Not Publish 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  37. DRAM Cell Area/Chip Size History / 2001 ITRS Model (3yr Node) (With FEP Data – 1998 ITRS Update) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  38. DRAM Cell Area/Chip Size History / 2001 ITRS Model (3yr-Node) (With SEMATECH Data) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  39. DRAM Cell Area/Chip Size History / 2003 ITRS 2yr-Node Model Proposal (With FEP Historical Data) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

  40. DRAM Cell Area/Chip Size History / 2003 ITRS 2yr-Node Model Proposal (With SEMATECHHistorical Data) 2002 ITRS Update Proposal – Work in Progress – Do Not Publish

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