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LAr calorimetry : new trigger system. New sommation card : layer 1 and 2 granularity preserved. Nouveau système déporté de lecture/traitement du signal de déclenchement. New backplanes for signal routing. New board : Digitization Former granularity restauration.
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LAr calorimetry : new trigger system New sommation card : layer 1 and 2 granularitypreserved Nouveau système déporté de lecture/traitement du signal de déclenchement. New backplanes for signal routing • New board: • Digitization • Former granularity restauration.
ADC development for new Local Trigger Digitizer Board (LTDB) • Successive Approximation Register (SAR) 12 bits ADC • IBM CMOS 130nm • Vdd @ 1.2V (Dig.) and 1.5V (An.) • Sampling frequency: 40 MSPS • About 25ns latency • Differential architecture (±1V) • Equivalent input capacitance: 6.4pF • Very low power consumption: • <10mW: 65% Analog + 35% Digital
2012 recap • 2 channels prototype : design ready in Spring. • Originally foresaw a production in May/August: • Several obstacles due to very severe layout constraints in IBM 130nm technology (new for micro electronic engineer). • Several exchanges with CERN & layout designer expert (SL3J). • Current version ready to be produced. Last checks with post-layout-simulations: still very promising. Next run in late October. Serial outputs ADC 12 bit 40MSPS Differential inputs MUX 12 bits Parallel ADC 12 bit 40 MSPS Differential inputs CLK distribution Serial outputs 40 MHz input clk
2012 recap : PEALL1 chip • First prototype • Production foreseen in late October 2012 Clk2out Data2out Output Codes Vin1 Valid2out Parallel output data Vin2 Clk1out Vref? Data1out Valid1out Trimming Input (Vpp) Select_ch Clk_smpl Post-Layout simulations
2013 plans • Chip test expected in Winter • Design of PEALL2, “final” chip suited for Atlas needs: • 4 channels, LVDS outputs. • Objective to submit the chip in May/August. Clk40MHz ClkFast1 Clk40MHz Clkread ADC 1 ADC 1 ∆Vin1 Dataout1 reg1 ∆Vin1 Dataout1 Validdata1 Validdata1 ADC 2 ADC 2 ∆Vin2 ∆Vin2 … reg2 … ADC 3 ADC 3 ∆Vin3 reg3 ∆Vin3 ClkFast4 ADC 4 ADC 4 ∆Vin4 Dataout4 ∆Vin4 Dataout4 reg4 Vref Validdata4 Validdata4 Vref
Delay impact wrt ATLAS plans • Currently 3 options considered in LAr collaboration: • LPSC SAR ADC • COTS option (TI) : radiation concerns • Columbia pipeline-SAR ADC: • First version of a pipeline 4 bits. • “final” version now designed. Production also scheduled in late October (originally planned in July). • TDR to be published in September 2013: • Tight schedule. • Apparently Columbia 1 version ahead LPSC but serious doubts about the feasibility to produce a fully working chip in one shot (Vref used for pipeline are especially touchy to deliver). • Moreover, Columbia design has serious drawbacks wrt LPSC option : power consumption, high frequency clock (640MHz) to be delivered (produced locally in LPSC chip). • LAr collaboration keeps 3 options open (especially in the design of the following chip in the chain).
Resources • 2012 production already paid (~14keuros, including design review, testing board). • 2013 production estimate: • PEALL1 irradiations: XXX keuros • 4 channels ADC production : 25 keuros • Design review 2 k euros • Testing board : 2 keuros • ~10 keuros remaining in 2012 group budget. Will need 19 keuros to cover the 2013 plans. • People: • 2 micro electronic engineer + 1 CR1 part time (10%) • 1 PhD student (starting 10/12). • Maybe a post doc (enigmass labex). Decision on Friday.
