CPSC 121: Models of Computation 2012 Summer Term 2

1. CPSC 121: Models of Computation2012 Summer Term 2 Building & Designing Sequential Circuits Steve Wolfman, based on notes by Patrice Belleville and others

2. Outline • Prereqs, Learning Goals, and Quiz Notes • Problems and Discussion • A Pushbutton Light Switch • Memory and Events: D Latches & Flip-Flops • General Implementation of DFAs (with a more complex DFA as an example) • How Powerful are DFAs? • Next Lecture Notes

3. Learning Goals: Pre-Class We are mostly departing from the readings to talk about a new kind of circuit on our way to a full computer: sequential circuits. The pre-class goals are to be able to: • Trace the operation of a deterministic finite-state automaton (represented as a diagram) on an input, including indicating whether the DFA accepts or rejects the input. • Deduce the language accepted by a simple DFA after working through multiple example inputs.

4. Learning Goals: In-Class By the end of this unit, you should be able to: • Translate a DFA to a corresponding sequential circuit, but with a “hole” in it for the circuitry describing the DFA’s transitions. • Describe the contents of that “hole” as a combinational circuitry problem (and therefore solve it, just like you do other combinational circuitry problems!). • Explain how and why each part of the resulting circuit works. Discuss point of learning goals.

5. Where We Are inThe Big Stories Theory Hardware How do we build devices to compute? Now: Learning to build a new kind of circuit with memory that will be the key new feature we need to build full- blown computers! (Something you’ve seen in lab from a new angle.) How do we model computational systems? Now: With our powerful modelling language (pred logic), we can prove things like universality of NOR gates for combinational circuits. Our new model (DFAs) are sort of full computers.

6. Outline • Prereqs, Learning Goals, and Quiz Notes • Problems and Discussion • A Pushbutton Light Switch • Memory and Events: D Latches & Flip-Flops • General Implementation of DFAs (with a more complex DFA as an example) • How Powerful are DFAs? • Next Lecture Notes

7. Problem: Push-Button Light Switch Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed. (Like the light switches in Dempster: Press and release, and the light changes state. Press and release again, and it changes again.) ?

8. A Light Switch “DFA” ? pressed light off light on pressed This Deterministic Finite Automaton (DFA) isn’t really about accepting/rejecting; its current state is the state of the light.

9. Problem: Light Switch Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed. Identifying inputs/outputs: consider these possible inputs and outputs: Input1: the button was pressed Input2: the button is down Output1: the light is on Output2: the light changed states • Which are most useful for this problem? • Input1 and Output1 • Input1 and Output2 • Input2 and Output1 • Input2 and Output2 • None of these ?

10. COMPARE TO: Lecture 2’s Light Switch Problem: Design a circuit to control a light so that the light changes state any time its switch is flipped. Identifying inputs/outputs: consider these possible inputs and outputs: Input1: the switch flipped Input2: the switch is on Output1: the light is on Output2: the light changed states • Which are most useful for this problem? • Input1 and Output1 • Input1 and Output2 • Input2 and Output1 • Input2 and Output2 • None of these ?

11. Outline • Prereqs, Learning Goals, and !Quiz Notes • Problems and Discussion • A Pushbutton Light Switch • Memory and Events: D Latches & Flip-Flops • General Implementation of DFAs (with a more complex DFA as an example) • How Powerful are DFAs? • Next Lecture Notes

12. Departures from Combinational Circuits MEMORY:We need to “remember” the light’s state. EVENTS:We need to act on a button push rather than in response to an input value.

13. Problem: How Do We Remember? We want a circuit that: • Sometimes… remembers its current state. • Other times… loads a new state to remember. Sounds like a choice. What circuit element do we have for modelling choices?

14. Worked Problem: “Muxy Memory” How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1. ??? 0 output new data 1 control We use “0” and “1” because that’s how MUXes are usually labelled.

15. Worked Problem: Muxy Memory How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1. old output (Q’) 0 output (Q) new data (D) 1 control (G) This violates our basic combinational constraint: no cycles.

16. Truth Table for “Muxy Memory” Fill in the MM’s truth table: a. b. c. d. e. None of these

17. Worked Problem: Truth Table for “Muxy Memory” Worked Problem: Write a truth table for the MM: Like a “normal” mux table, but what happens when Q'  Q?

18. Worked Problem: Truth Table for “Muxy Memory” Worked Problem: Write a truth table for the MM: Q' “takes on” Q’s value at the “next step”.

19. “D Latch” Symbol + Semantics We call a “muxy memory” a “D latch”. When G is 0, the latch maintains its memory. When G is 1, the latch loads a new value from D. old output (Q’) 0 output (Q) new data (D) 1 control (G)

20. D Latch Symbol + Semantics When G is 0, the latch maintains its memory. When G is 1, the latch loads a new value from D. old output (Q’) 0 output (Q) new data (D) 1 control (G)

21. D Latch Symbol + Semantics When G is 0, the latch maintains its memory. When G is 1, the latch loads a new value from D. D new data (D) Q output (Q) control (G) G

22. Hold On!! Why does the D Latch have two inputs and one output when the mux inside has THREE inputs and one output? • The D Latch is broken as is; it should have three inputs. • A circuit can always ignore one of its inputs. • One of the inputs is always true. • One of the inputs is always false. • None of these (but the D Latch is not broken as is).

23. Using the D Latch for Circuits with Memory Problem: What goes in the cloud? What do we send into G? CombinationalCircuit to calculatenext state D ?? Q input G We assume we just want Q as the output.

24. Using the D Latch for Our Light Switch Problem: What do we send into G? current light state D ?? Q no (0 bit) input output G • T if the button is down, F if it’s up. • T if the button is up, F if it’s down. • Neither of these.

25. A Timing Problem:We Need EVENTS! Problem: What do we send into G? current light state “pulse” when button is pressed D Q output G button pressed As long as the button is down, D flows to Q flows through the NOT gate and back to D...which is bad!

26. A Timing Problem, Metaphor(from MIT 6.004, Fall 2002) What’s wrong with this tollbooth? P.S. Call this a “bar”, not a “gate”, or we’ll tie ourselves in (k)nots.

27. A Timing Solution, Metaphor(from MIT 6.004, Fall 2002) Is this one OK?

28. A Timing Problem Problem: What do we send into G? current light state “pulse” when button is pressed D Q output G button pressed As long as the button is down, D flows to Q flows through the NOT gate and back to D...which is bad!

29. A Timing Solution (Almost) D D Q Q Never raise both “bars” at the same time. output G G button pressed

30. A Timing Solution D D Q Q ?? output G G The two latches are never enabled at the same time (except for the moment needed for the NOT gate on the left to compute, which is so short that no “cars” get through).

31. A Timing Solution D D button press signal Q Q output G G button pressed

32. Button/Clock is LO (unpressed) 1 1 0 1 D D Q Q output LO 0 G G We’re assuming the circuit has been set up and is “running normally”. Right now, the light is off (i.e., the output of the right latch is 0).

33. Button goes HI (is pressed) 1 1 0 1 D D Q Q output HI 1 G G This stuff is processing a new signal.

34. Propagating signal.. left NOT, right latch 1 1 1 0 D D Q Q output HI 1 G G This stuff is processing a new signal.

35. Propagating signal.. right NOT (steady state) 0 1 1 0 D D Q Q output HI 1 G G • Why doesn’t the left latch update? • Its D input is 0. • Its G input is 0. • Its Q output is 1. • It should update!

36. Button goes LO (released) 0 1 1 0 D D Q Q output LO 0 G G This stuff is processing a new signal.

37. Propagating signal..left NOT 0 1 1 1 D D Q Q output LO 0 G G This stuff is processing a new signal.

38. Propagating signal..left latch (steady state) 0 0 1 1 D D Q Q output LO 0 G G And, we’re done with one cycle.How does this compare to our initial state?

39. Master/Slave D Flip-Flop Symbol + Semantics When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D. Otherwise, it maintains its current value. new data (D) D D output (Q) Q Q control or “clock” signal (CLK) G G

40. Master/Slave D Flip-Flop Symbol + Semantics When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D. Otherwise, it maintains its current value. new data (D) D D output (Q) Q Q control or “clock” signal (CLK) G G

41. Master/Slave D Flip-Flop Symbol + Semantics When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D. Otherwise, it maintains its current value. new data (D) D D output (Q) Q Q control or “clock” signal (CLK) G G

42. Master/Slave D Flip-Flop Symbol + Semantics When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D. Otherwise, it maintains its current value. output clock signal Q new data D We rearranged the clock and D inputs and the output to match Logisim.Below we use a slightly different looking flip-flop.

43. Why Abstract? Logisim (and real circuits) have lots of flip-flops that all behave very similarly: • D flip-flops, • T flip-flops, • J-K flip-flops, • and S-R flip-flops. They have slightly different implementations… and one could imagine brilliant new designs that are radically different inside. Abstraction allows us to build a good design at a high-level without worrying about the details. Plus… it means you only need to learn about D flip-flops’ guts.The others are similar enough so we can just take the abstraction for granted.

44. Outline • Prereqs, Learning Goals, and !Quiz Notes • Problems and Discussion • A Pushbutton Light Switch • Memory and Events: D Latches & Flip-Flops • General Implementation of DFAs (with a more complex DFA as an example) • How Powerful are DFAs? • Next Lecture Notes

45. How Do Computers Execute Programs? • High-level languages (Java/Racket) are translated into low-level machine language • A machine language program is a list of instructions in a representation scheme close to “plain” binary (e.g., 4 bits for the type of instruction, 4 bits for what part of the computer the result goes to, etc.) • Each instruction has a (barely) human-readable version • After it’s done with an instruction, the computer (usually) executes the next instruction in the list

46. Simplified Example(sum of 1..n) • sum  0 • is n = 0? • if the answer was yes, go to (7) • sum  sum + n • n  n - 1 • go to (2) • halt If the computer executed all instructions in order, there’d be no loops or recursion! Fortunately, “branch” instructions (like (3)) tell the computer to go elsewhere.

47. Simplified Example, Complicated Execution • sum  0 • is n = 0? • if the answer was yes, go to (7) • sum  sum + n • n  n - 1 • go to (2) • halt To run faster, the computer starts executing one instruction even before it finishes the last. But then what does it do with (3)?Does it execute (4) or (7)?

48. Branch Prediction Machine To pre-execute a “branch”, the computer guesses which instruction comes next. Here’s one reasonable guess: If the last branch was “taken” (like going to (7) from (3)), take the next. If it was “not taken” (like going to (4) from (3)), don’t take the next. Why? In recursion, how often do we hit the base case vs. the recursive case?

49. Implementing the Branch Predictor (First Pass) Here’s the corresponding DFA. (Instead of accept/reject, we care about the current state.) taken  the last branch was taken not taken  the last branch was not taken yes  we predict the next branch will be taken no  we predict the next branch will be not taken nottaken taken taken no yes nottaken Experiments show it generally works well to add “inertia”so that it takes two “wrong guesses” to change the prediction…

50. Implementing the Branch Predictor (Final Version) Here’s a version that takes two wrong guesses in a row to admit it’s wrong: Can we build a branch prediction circuit? taken taken taken no? YES! taken nottaken nottaken yes? nottaken NO! not taken