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計算機アーキテクチャ演習第6回 PICO の Verilog 記述

計算機アーキテクチャ演習第6回 PICO の Verilog 記述. 慶応大学 天野. MUX. MUX. MUX. MUX. MUX. PICO の構成(前期の図を若干変更). regc. aluout. outc. op. pc. ir. com. op2. ALU. op. 110 001. alubin. aluain. Expander. ‘2’. regb. op2. rega. dest. adrA. src. adrB. idata. regfile. ddatain. ddataout. we_.

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計算機アーキテクチャ演習第6回 PICO の Verilog 記述

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  1. 計算機アーキテクチャ演習第6回PICOのVerilog記述計算機アーキテクチャ演習第6回PICOのVerilog記述 慶応大学 天野

  2. MUX MUX MUX MUX MUX PICOの構成(前期の図を若干変更) regc aluout outc op pc ir com op2 ALU op 110 001 alubin aluain Expander ‘2’ regb op2 rega dest adrA src adrB idata regfile ddatain ddataout we_ Instruction Memory Data Memory iadr dadr

  3. レジスタファイル module regfile (clk, adrA, adrB, inc, outa, outb, rwe); `include "pico.h" input clk; input [RegNum-1:0] adrA, adrB; input [DataBus-1:0] inc; output [DataBus-1:0] outa, outb; input rwe; reg [DataBus-1:0] rfile [0:7]; assign outa = rfile[adrA]; assign outb = rfile[adrB]; always @(posedge clk) if (rwe) rfile[adrA] <= inc; endmodule 初期化は特に必要ない。 rwe=Hの時、同期的に書き込み 読み書きは同時に可能

  4. 状態遷移 結果を書き込む命令 それ以外:分岐、STなど IF RF EX WB 演算実行 飛び先セット メモリからの読み 書き込み irに命令を フェッチ レジスタ 読み出し PC←PC+2 結果の格納

  5. 状態遷移、レジスタの記述 always@(posedge clk) if(reset_== Enable_) begin pc <= 16'h0000; ir <= 16'h0000; stat <= IF; end else case (stat) IF: begin ir <= idata; stat <= RF; end RF: begin pc <= aluout; rega <= outa; regb <= outb; stat <= EX; end EX: begin if(pcset) pc <= aluout; if(wbinst) begin regc <= outc; stat <= WB; end else stat <= IF; end WB: stat <= IF; endcase リセット時 レジスタの値設定を、statの変化と 共に記述している wbinst: 結果を書き込む命令 pcset: 分岐成立

  6. One-Hot Counter parameter IF = 4'b0001; parameter RF = 4'b0010; parameter EX = 4'b0100; parameter WB = 4'b1000; parameter RF_BIT = 2'b01; parameter EX_BIT = 2'b10; parameter WB_BIT = 2'b11; stat[EX_BIT]は、状態がEXの時だけ1になる。他もこれと同じ→One Hot Counterの特性の利用

  7. 入出力、レジスタ module bpico16 (clk, reset_, iaddr, idata, daddr, ddatain, ddataout, dwe); `include "pico.h" input clk, reset_; output [AddrBus-1:0] iaddr; input [DataBus-1:0] idata; output [AddrBus-1:0] daddr; input [DataBus-1:0] ddatain; output [DataBus-1:0] ddataout; output dwe; // Registers reg [AddrBus-1:0] pc; reg [DataBus-1:0] ir; reg [DataBus-1:0] rega, regb, regc; reg [StateNum-1:0] stat;

  8. 信号線、命令フィールド定義 wire pcset; wire rwe; wire [DataBus-1:0] aluout, result, outa, outb, outc ; wire [DataBus-1:0] aluina, aluinb; wire [ComNum-1:0] com; //Field wire [Opcode-1:0] op, op2; wire [RegNum-1:0] dest,src; // Instructions wire wbinst; wire brinst; wire imm16; assign op = ir[15:11]; assign dest = ir[10:8]; assign src = ir[7:5]; assign op2 = ir[4:0];

  9. 命令デコード assign wbinst = ((op == ROP) & ( (op2[4:3] == 2'b00) | op2 == LD) ) | (op == LDLI ) | (op == LDHI) | (op[4:3] == 2'b00)&(op != ROP) ; assign brinst = (op == BNEZ) | (op == BEQZ); assign pcset = ( (rega == 16'h0000)&(op == BEQZ)| (rega != 16'h0000)& (op == BNEZ) );

  10. MUX メモリ周辺 assign iaddr = pc; assign ddataout = regb; assign dwe = (stat[EX_BIT] & (op== ROP) & (op2== ST)) ; assign daddr = ((op==ROP) & (op2 == ST))? rega : regb ; idata ddatain regb ddataout we_ rega Instruction Memory Data Memory iadr dadr regb

  11. MUX MUX MUX MUX ALU周辺 assign aluina = (stat[RF_BIT] | brinst) ? pc : rega; assign imm16 = ((op[4:3] == 2'b00 & op != ROP) | brinst | op == LDLI | op == LDHI) ; assign aluinb = stat[RF_BIT] ? 16'h0002 : imm16 ? { {8{ir[7]}}, ir[7:0] } : op == LDHI ? {ir[7:0],8'h00} : regb; assign com = stat[RF_BIT] | brinst ? ADDOP : (op == LDLI | op == LDHI) ? THB : imm16 ? op[2:0] : op2[2:0]; assign outc = ( op == ROP & op2 == LD) ? ddatain: aluout ; assign aluout = alu(aluina, aluinb, com); regc aluout outc com ALU alubin aluain ‘2’ Expander pc regb rega

  12. レジスタファイル周辺 assign rwe = stat[WB_BIT] & wbinst; regfile reg0(.clk(clk), .adrA(dest), .adrB(src), .inc(regc), .outa(outa), .outb(outb), .rwe(rwe)); regb rega adrA adrB regc

  13. 演習 1.LDHI rd,#X rd <-X,0x00 11101 ddd xxxxxxxx Load High Immediate LDHI命令を付け加えよ。 2.JMP X PC<-PC+0x100 01111 00100000000 Jump JMP命令を付け加えよ。

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