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EXL/R3B Calorimeters- Readout from ASIC to DAQ

EXL/R3B Calorimeters- Readout from ASIC to DAQ. Ian Lazarus STFC Daresbury Laboratory. Overview: What makes ASICs “application specific”? ASIC Readout Options Using timestamps Connections to DAQ An example from AIDA (DeSpec) Summary. What makes an ASIC “application specific”?

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EXL/R3B Calorimeters- Readout from ASIC to DAQ

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  1. EXL/R3B Calorimeters- Readout from ASIC to DAQ Ian Lazarus STFC Daresbury Laboratory

  2. Overview: • What makes ASICs “application specific”? • ASIC Readout Options • Using timestamps • Connections to DAQ • An example from AIDA (DeSpec) • Summary

  3. What makes an ASIC “application specific”? • Detector characteristics: • Geometry (pad pitch, channel count) • Detector Capacitance • Leakage current • Gain required • Signal processing required (shaping time depends on detector type and size) • Other things can usually be standardised • readout (but can be analogue or digitised in ASIC) • triggering • slow control (e.g. I2C) • power supplies

  4. ASIC Readout options • Analogue • Shaper output (with or without peak detector)- 1 or 2 pads/channel • Multiplex to an external ADC; read peak detector outputs • Preamplifier output (for external Flash ADC) • Digital • Multiplex to an internal ADC; read digital data • Examples…

  5. Analogue readout, 2 pads per channel. Example- FREDA. 16 channels Peaking times: 50-240ns Gain: x1,2,4 or 8 16 inputs 16 diff outputs Design is pad-limited. Aimed at gas detectors with Cdet in range 2-80pF

  6. Multiplex to ext. ADC; read peak detector outputs Example- Gassiplex (CERN) Peaking times: 400-1000ns Gain: 4.9mV/fC 16 inputs 1 mux output Reads all 16 channels in turn (10 MHz max; CAEN V550 max is 5MHz)) Aimed at Si/gas detectors

  7. Preamplifier output (for external Flash ADC) Example- 8 AIDA ASIC. Octal Flash ADC 12/14 bit 50MHz PSA Spectroscopy ADC

  8. Multiplex to an internal ADC; read digital data Example- NUCAM • 128 inputs, each with: • Preamp • Programmable Shaper • Peak time measurement • Discriminator • Programmable leakage comp. • Intelligent multiplexer • Common ADC (12 bits 1MHz) • 4 bit daisy chained readout • Readout 32 bits/channel in 1us • Read only active channels

  9. Example of readout rates. Time to read 128 channels of which 3 are active. Assume 5MHz readout for analogue multiplexers

  10. Using Timestamps. • Multiplexers cause problems • either slow (read all channels) and timestamp at low rate. • or lose timing relationship with inputs • Two possible solutions • Timestamp in ASIC before multiplexer • Good timing correlation • But, need clock in ASIC near detector so need careful layout to avoid noise problems. • Also need to reconstruct full timestamp after ASIC (or read huge amounts of un-necessary data). • Use multi-channel FADC (e.g. octal AD9252) with FPGA to process one channel per pin ASIC preamps. • Difficult for fast detectors due to limited speed of octal FADCs

  11. Example of timestamp in an ASIC.

  12. Readout from ASIC • Requirements: • ADC: • either external ADC matched to mux clock rate • or Internal ADC in ASIC • or ADC per output for non-muxed ASIC • Control logic (sequencing, clocks, ext ADC) • Timestamp control and logic • Fast Data path • NUSTAR Interfaces (slow control, timestamp, readout)

  13. Usually control readout from FPGA (Field programmable gate array). Why? • Flexible (reprogrammable in situ to change function or fix bugs) • Fast (>1Gbyte/sec using multiple output paths) • Handles control logic and clocks easily • Handles data transfer easily and fast • Built in IP for Ethernet (Virtex 4) and PCIe (Virtex 5) • Reasonable expectation of common development (shared IP) for NUSTAR interfaces to slow control, readout and BUTIS timestamping.

  14. Part of FPGA Octal FADC (serial out) 12/14bit 50MHz (2 per ASIC) Octal FADC (serial out) 12/14bit 50MHz (2 per ASIC) Pk Det & Mux Preamp + shaper low/high gain. (16 channels) Sliding Scale Spectroscopy ADC 14bits 1 to 5us conv. Control Logic

  15. 128 detector signals in; 1 data fibre out (max 50Mbytes/sec) or multiple MGTs with PCIe or point-point 200Mbytes/sec 16 FADCs (12/14 bit) 1 Sliding Scale ADC (14bit) per ASIC 16 ch ASIC Virtex 4LX FPGA Fibre Driver (Laser) ASIC 16 FADCs Virtex 4FX FPGA (or V5) 1 SS ADC ASIC 16 FADCs ADC Readout 1 SS ADC PPC (Unix) Timestamp control ASIC 16 FADCs Ethernet physical interface ASIC Control 1 SS ADC ASIC Slow Control 16 FADCs 1 SS ADC Virtex 4LX FPGA ASIC 16 FADCs MGT (raw/PCIe) 1 SS ADC ASIC 16 FADCs 1 SS ADC ADC Readout ASIC 16 FADCs Timestamp control FADC PSA 1 SS ADC ASIC Control ASIC 16 FADCs Data Output Slow Control 1 SS ADC

  16. Summary: • Multiplexing is good for high channel counts, but makes timestamping more complex and slows down readout. • For more simple timestamping consider high density FADC and pad per channel. • DAQ links will use FPGAs for maximum flexibility and to take advantage of shared developments to NUSTAR standards (1G (10G?) Ethernet, PCIe)

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