Backplane Design and Optimization Using 28nm FPGAs

1. Backplane Design and Optimization Using 28nm FPGAs Technology Roadshow 2011

2. Agenda • Backplane Challenges • 28-nm Transceiver Architecture & Signal Integrity Features • Simulation Tools, Models and Flows • 10GBASE-KR Backplane Design Example • Backplane Solutions • Summary

3. 10+ Gbps Backplane Design Challenges

4. Backplane Applications • Enterprise switching • Line card and switch fabric • Core switch • Aggregation • Cross-bar applications • Shared memory architecture • Access boxes • DSLAM, PON • T1, E1, cable • Proprietary backplanes/midplanes • Time-slot interchange (TSI) • Transport • Next-generation Ethernet switching • Types of transport • ROADM • OTN WDM • MSPP • Broadcast switching • Serial digital interface (SDI) aggregation

5. 10GBASE-KR Backplane Electrical • TX • Eye mask • Channel • Channel description • Insertion loss • Return loss • RX • Jitter Tolerance • Return loss • System • BER =<1E-12

6. 28-nm Transceiver Architecture & Signal Integrity Features

7. Stratix V Transceiver Block Architecture Clock networks Fractional PLLs (fPLL) • Up to 66 full-duplex transceiversat 14.1 Gbps • Scalability and flexibility with continuous bank of transceivers with complete PMA and PCS per channel • Multiple transmitter (TX) PLL sources • More LC oscillators • Programmable LC tuning range • Multipurpose fractional PLLs (fPLLs) for additional TX clock source • Analog PLL-based CDR per receive channel • Advanced TX and receiver (RX) equalization for 14.1-Gbps backplane support • Including 10GBASE-KR • Optimized PCS / Hard IP for multiple protocol support • Additional 28G transceivers Hard PCS Embedded HardCopy Block) Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA LC Transmit PLLs Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA . . . .

8. Dedicated Circuitry for Advanced Signal Conditioning • LC PLL for sub-ps transmit jitter • Analog-PLL CDR for improved jitter tolerance • 4-tap pre-emphasis and linear equalization for 14.1-Gbps backplane applications • Advanced signal conditioning including 5-tap DFE and ADCE • Mitigate backplane losses and crosstalk • Targeted 10GBASE-KR and CEI-11G electricals Analog CDR LC TX PLL RX TX Pre-Emphasis EQ CDR Backplane Channel: Including 10GBASE-KR

9. Arria V Transceiver Architecture . . . . • Scalability and flexibility through a continuous bank of transceivers • Complete physical medium attachment (PMA)+ physical coding sublayer (PCS) per channel • Unused channels can be utilized as clock multiplier unit (CMU) PLLs • Flexible transmit clock sources enable up to 24 independent data rates in a single device Clock Networks Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA Hard PCS Transceiver PMA . . . . Arria V FPGAs Offer Up to 36 Full-Duplex Transceiver Channels with PCS and PMA

10. Altera 28nm Transceiver Summary

11. Simulation Tools, Models and Flows

12. Transceiver Simulation Models • Altera’s suite of transceiver design tools • Evaluate performance in custom application • Run “What if” simulations for early analysis • Create design constraints in layout and design • Run in-system verification for board bring-up and live debug • HSPICE full circuit models • IBIS-AMI behavioral models • Fast simulation • Analog and algorithmic description of all major transceiver components • Analysis of millions of bits

13. TX model RX model Customer provided S-parameters PELE Coefficients Backplane PELE – Pre-emphasis/Equal Link Estimator • Optimize the equalization coefficients for the transceiver • Early estimate of link performance • Inputs: Channel / settings

14. Simulation Model Comparison

15. HST Jitter and BER Estimator • Custom characterization • Quickly and accurately estimatesystem link reliability (BER) • Utilize customer-specific channel (S-Parameter) • Run statistical analysis using characterization data • Margin analysis • TX • RX • Channel • Reduction of system cost • Cost-effective alternatives for the same system performance Currently Available for Stratix IV and V FPGAs

16. Link Simulation Flow – Early Stage • Use generic S-parameter file • From backplane model provider, EDA simulation tool extraction or VNA measurement • Use PELE/JBE to see if the selected device compensates channel losses using pre-emphasis or equalization, or both • Check to see if the eye opening meets the protocol requirements or device requirements • Proceed to device selection Generic S-Parameters (model provider/fab) PELE/HST JBE No Eye Mask Requirements Yes Device Selection (TX and RX)

17. Link Simulation Flow – Design Phase • Device selection • Channel design • Further analysis • Pre-emphasis and/or equalization settings selection • Fine tune/validate settings • HSPICE • IBIS-AMI behavioral models • Use JBE to include the statistical data • Use the transceiver toolkit to verify and debug Channel Design Extract BackplaneS-Parameters PELE EDA Simulations(Fine-tune/Validate Settings) Yes Include StatisticalData (RJ)? No HST JBE No Eye MaskRequirements Yes Board Design Use Transceiver ToolkitDebug/Verification

18. 10GBASE-KR Backplane Design Example

19. Standalone mathematical tool Requires MATLAB run-time library Inputs Data rate VOD Backplane TX pre-emphasis setting RX equalization setting AC gain (CTLE) DC gain DFE Outputs Deterministic eye opening at TX, RX, and post equalization Optimal pre-emphasis and equalization setting PELE Configuration Auto/Manual Mode Stratix V GX PELE Tool Backplane (*.s4p) Pre-emphasis Data Rate Equalization VOD Eye Opening

20. Standalone mathematical tool Requires MATLAB run-time library Inputs Data rate: 10.3125 Gbps VOD : 1000 mV Backplane: “30inches_2connectors_backplane.s4p” TX pre-emphasis setting: Auto RX equalization setting AC gain (CTLE) : Auto DC gain: 4 (0-8 dB) DFE: Auto Outputs Deterministic eye opening at TX, RX, and post equalization Optimal pre-emphasis and equalization setting PELE Configuration Auto/Manual Mode Stratix V GX PELE Tool Backplane (*.s4p) Pre-emphasis Data Rate Equalization VOD Eye Opening

21. PELE Simulation (30” link @10.3125G) TX

22. PELE Simulation Output • Refer to Stratix V user guide on PELE instructions • PELE output results: Starting point for optional simulation analysis 0.75 UI = deterministic eye opening 1- 0.75 UI = 0.25 UI = non compensated jitter

23. 10GBASE KR Requirements RX TX • TX Jitter Characteristics • RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 • Overall TJTX < 0.28 UI = 27ps @ 10.3125 Gbps • Channel Characteristics • Insertion loss < 25dB @ 5.15625 GHz • Altera RX Requirements – Post EQ • Eye width > 0.6 UI • Eye height > 100mV • RX Jitter Tolerance Requirements • SJ > 0.115, RJ > 0.13, DCD > 0.130 • System Performance • BER = 1E-12 10GBASE-KR channel 3 1 2 4 EQ CDR 5

24. Transmitter RX TX • 10GBASE-KR transmit jitter requirements • RJ < 0.15 UI, DJ < 0.15, DCD < 0.035 • Overall TJTX < 0.28 UI = 27ps @ 10.3125 Gbps • PELE Eye opening @ TX output • TX TJ = 1- Eye opening at TX output • = 1-0.92313 = 0.07687 UI • < 0.185 UI (DJ + DCD)

25. Backplane Channel RX TX • Channel: • Length: 30” • Connectors: 2 • Loss @ 5.15 GHz: • Approx -20dB • 10GBASE-KR Insertion loss spec: < 25dB @ 5.15625 GHz

26. Receiver RX TX • RX Jitter Tolerance Requirements • SJ > 0.115, RJ > 0.13, DCD > 0.130 • Altera data sheet and characterization report • Altera RX Requirements at 10.3125Gbps • Deterministic eye opening

27. System Performance RX TX TX • PELE analysis is a deterministic simulator • Jitter and BER Estimator (JBE) incorporates random jitter components of transmitter and receiver through characterized data • Early version (EAP) of Stratix V JBE is based on Stratix IV data • Final version will incorporate actual silicon measurement • JBE will determine Bit Error Ratio performance of link

28. Jitter and BER Estimator Tool

29. JBE Configuration Steps Step1 • Setup global parameters • Target BER • Data Rate (Gbps) • Test Pattern • Link configuration • Analysis mode selection/eye mask setup • Options: Full Link, TX, RX Step 2

30. JBE Configuration Steps • Configure TX settings • Configure RX settings • Input the non-equalized channel DJ from PELE simulation output • “1 – Eye opening” post equalization • May add margin to this number to account for cross-talk Step 4 Step 3 Step 5

31. Link Analysis: Full Link Mode • Full link simulation shows that the link meets the BER target of 10-15 • Margin analysis

32. Backplane Solutions

33. 10GBASE-KR Backplane PCS • Auto-negotiation • Link Training • Forward Error Correction • MoreThanIP offers a complete PCS solution for 10GBASE-KR applications for Stratix V

34. Connectors • Major component of link reliability • Evaluation of link includes • Insertion Loss • Return Loss • Crosstalk • Advanced EDA simulationtools • Hardware analysis

35. From linear equalizer To CDR _ Z-1 C1 Z-1 C2 Z-1 C3 Z-1 C4 Z-1 C5 Stratix V 5-Tap Decision Feedback Equalizer • Improves signal-noise-ratio (SNR) • With CTLE, addresses pre-cursor and post-cursor ISI • Mitigates the effects of crosstalk • Automatically adapts to PVT conditions

36. Stratix V FPGA EyeQ Eye Viewer • View receiver signal margin with Altera’s EyeQ® eye viewer • Complete vertical and horizontal reconstruction of eye opening • Uninterrupted data path for live debug capability EyeQ® Pre-Emphasis EQ CDR Lossy medium Rx Tx Minimize board bring up / debug time with Dynamic reconfiguration and EyeQ

37. Summary • Link simulation flow enabled through Altera simulation tools and models • 10GBASE-KR backplane system performance achieved • Altera offers complete solution for 10+ Gbps backplane analysis and design Stratix V FPGAs offer the optimum platform for 10Gbps+ backplane systems

38. Thank You Backplane Design and Optimization Using 28-nm FPGAs