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Front-End Electronics for PHENIX Time Expansion Chamber

Front-End Electronics for PHENIX Time Expansion Chamber. W.C. Chang Academia Sinica, Taipei 11529,Taiwan A. Franz, J. Fried, J. Gannon, J. Harder, A. Kandasamy, M.A.Kelley, J.Mahon, S.Mioduszewski, E.O’Brien, P.O’Connor, R. Pisani, S.Rankowitz, W. Von Achen

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Front-End Electronics for PHENIX Time Expansion Chamber

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  1. Front-End Electronics for PHENIX Time Expansion Chamber W.C. Chang Academia Sinica, Taipei 11529,Taiwan A. Franz, J. Fried, J. Gannon, J. Harder, A. Kandasamy, M.A.Kelley, J.Mahon, S.Mioduszewski, E.O’Brien, P.O’Connor, R. Pisani, S.Rankowitz, W. Von Achen Brookhaven National Lab, Upton, NY 11973 A.Lebedev, M. Rosati Iowa State University, Ames, Iowa 50011 K.Barish, T. Ferdousi, S.Y. Fung, D. Kotchetkov, X.H.Li, M. Muniruzzaman, B. Nandi, R. Seto, H.Q. Wang, W. Xie University of California – Riverside, CA 92521 O. Dietzsch, E.M. Takagui Universidade de Sao Paulo, Sao Paulo, Brazil

  2. TEC performs charged particle tracking, ID at RHIC/PHENIX, Brookhaven National Lab

  3. ElectronicsRequirements drift space 3cm mm/usec: 25 (P-10 gas) or 15 (Xe-based) dual gain: dE/dx 0.16 keV/mm (8 fC in 25 nsec) TR photon 10 keV (300 fC in 100 nsec) diverse operation: Au-Au at s1/2=200 AGeV - high multiplicity p-p at s1/2=500 GeV - high trigger rate (25 kHz)

  4. TEC electronics chain

  5. Preamplifier/Shaper ASIC • unipolar, 70 nsec, CR-RC4shaper • ion tail cancellation • trans-impedance amplifier: 75k • active baseline restoration • split gain: 1X (TR), 5X (dE/dx) • selectable gain, shaping time, tail cancellation • channel calibration capacitor & disable

  6. Preamplifier/Shaper board poly-resettable fuse external ESD protection preamp input programmable DAC for calibration receive configuration, calibration data from FEM drive back analog signals differentially

  7. TEC Preamplifier/Shaper

  8. Flash-ADC ASIC 2 internal ADC’s cover 2 signal ranges sample rate: 40M per sec common encoder selectable coding for each ADC

  9. dE/dx TR 2 signal ranges 5-bit output with 9-bit range optimum resolution without many comparators

  10. Digital Memory Unit level 1 latency buffer: 1-190 clock delay length 5 event FIFO memories, 4 channels/chip 2-80 clock event length programmable delay, event length test data input data reformatter input: 80 serial data words with 4 channels/word output: [20 serial words/channel with 4 tics/word] x 4 channels

  11. Diagnostic: status & control words added to data stream (headers & trailers)

  12. Time Interface Card receive 20-bit timing & control drive to FEM’s via back-plane BeamClkX4: accurate timing reference BeamClk: phase, beam crossing control signals: module address, node ID, endat reset level 1 counter in serial control

  13. TEC Front-End Module

  14. Testing & Performance automated test fixtures P/S ASIC: INL: <1% (dE/dx), <3% (TR) channel cross-talk <2% ESD test: spark at 100 uJ, 1 Hz with external protection, survived over 1000 sparks Flash -ADC ASIC: operating range: 80oC, 50 MHz INL +0.03 LSB rms (dE/dx) INL better than –0.004 LSB (TR) FEE noisewithin specification: 0.3 fC/channel rms in lab coherent 1-2 fC/channel rms in experiment

  15. TEC FEE chain test GTM: low jitter, timing, readout enable strobe DCM: receive data, send busy

  16. calibration pulse triggered by strobe interval 16 time buckets readout match settings 9.7 MHZ sine wave readout match input

  17. Summary custom TEC FEE for over 20k channels 3 custom ASIC’s: P/S, Flash-ADC, DMU 500, 32-channel P/S boards 240, 64 channel FEM’s 10 Timing Interface Cards diagnostic, remote communication optical data transmission already: readout dE/dx at PHENIX next year: readout dE/dx & TR

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