RISC

1. x86 RISC CISC

2. Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures Emily Blem, JaikrishnanMenon, and KarthikeyanSankaralingam

3. x86 x86 x86 What role if any does RISC vs. CISC play in this power struggle? RISC & CISC RISC RISC & CISC CISC

4. ISA being RISC or CISC does not matter for modern microprocessors

5. Overview • Methods • 11 Key Findings • 6 on performance • 3 on power • 2 on power/performance tradeoffs • Conclusion

6. Overview • Methods • 11 Key Findings • 6 on performance • 3 on power • 2 on power/performance tradeoffs • Conclusion

7. Platforms Intel Atom N450 BeagleBoard ARM Cortex A8 Linux 2.6 Intel Sandy Bridge Core i7 PandaBoard ARM Cortex A9 GCC

8. Workloads Desktop Mobile Server Lighttpd CLucene Database kernels CoreMark WebKit SPEC CPU2006 / 37

9. Measurements • Performance measurement on real hardware • Extensive use of performance counters • Cycles, instructions, cache misses, branch misses… • Power measurements using Wattsup meters

10. Overview • Methods • 11 Key Findings • 6 on performance • 3 on power • 2 on power/performance tradeoffs • Conclusion

11. But first… “Iron Law of Performance” – Clark What is performance?

12. Performance (130) (72) (24) (344) Key Finding 1 Large performance differences due to varying clock frequencies and core characteristics

13. Cycle counts Key Finding 2 Cycle count differences are less than 2.5X

14. Instruction counts Macro-op counts are nearly same across ARM and x86 Key Finding 3 CPI is lessfor x86 implementations

15. Instruction Mix Key Finding 4 ISA effects are indistinguishable

16. Key Findings Large performance gaps across cores After accounting for clock frequency, performance gaps within 2.5X CPI is lessfor x86 implementations ISA effects are indistinguishable

17. Why are performance gaps present? Instruction Count Cache Related Branch Related Issue Width Related Benchmarks

18. Case study: omnetpp Key Finding 5 Performance gaps due to microarchitecture ISA Effect: ARM has 4% more instructions Microarchitecture Effect 2: A9 experiences 15x more instruction cache misses Microarchitecture Effect 3: A9’s issue width is half that of i7’s Microarchitecture Effect 1: A9 experiences 29x more branch mispredictions

19. Key Findings • Large performance gaps across cores • After accounting for clock frequency, performance gaps within 2.5X • CPI is lessfor x86 implementations • ISA effects are indistinguishable • Performance gaps due to microarchitecture • RISC or CISC choice does not play a role in performance-driving µarch decisions • Details in paper

20. Power and Energy Large performance gaps across cores After accounting for clock frequency, performance gaps within 2.5X CPI is lessfor x86 implementations ISA effects are indistinguishable Performance gaps due to microarchitecture RISC or CISC choice does not play a role in performance-driving µarch decisions x86 implementations are higher power – dictated by performance targets Power consumption is tied to microarchitecturaldesign decisions Energy consumption also tied to microarchitectural design decisions

21. Power-Performance Tradeoffs Key Finding 10 Regardless of ISA, processors follow cubic power/performance trends

22. Energy-Delay analysis Considering ED, A15 is 46% lower than any other design we considered. Considering ED>1.4, i7 is best Considering ED2, i7 is more than 2X better than next best design Key Finding 11 Microarchitecture and design choices are key – not the ISA

23. Conclusion ISA being RISC or CISC does not matter for power and performance of modern processors.

24. What is the ISA’s role? • Supporting specialization • AVX crypto, Virtualization extensions • Jazelle DBX, ARM Trustzone… • Exposing more workload-specific semantic information to the substrate • Transactional Memory support • Reliability-oriented extensions • Many more…

25. Questions? Additional resources (detailed report and raw data spreadsheet) available at - http://research.cs.wisc.edu/vertical/isa-power-struggles