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TMS320

A.A.2009-10. Overview. TMS320. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004. Digital Signal Processor. VoIP. Texas Instruments’ TMS320 Family. C2000. C5000. Performance & Best Ease-of-Use. Efficiency Best MIPS per Watt / Dollar / Size - Wireless phones

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TMS320

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  1. A.A.2009-10 Overview TMS320 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004

  2. Digital Signal Processor VoIP Texas Instruments’TMS320 Family C2000 C5000 Performance & Best Ease-of-Use Efficiency Best MIPS per Watt / Dollar / Size - Wireless phones - Internet audio players - Digital still cameras - Modems - Telephony - VoIP - Multi Channel and Multi Function App's - Comm Infrastructure - Wireless Base-stations - DSL - Imaging - Multi-media Servers - Video Lowest Cost Control Systems - Motor Control - Storage - Digital Ctrl Systems C6000 A.A.2009-10

  3. Digital Signal Processor C6000 c62x:Thesefirst-generation fixed-point DSPsrepresent breakthrough technology that enables new equipments and energizes existing implementations for multi-channel, multi-function applications, such as wireless base stations, remote access servers (RAS), digital subscriber loop (xDSL) systems, personalized home security systems, advanced imaging/biometrics, industrial scanners, precision instrumentation and multi-channel telephony systems. C64x:The C64x fixed-point DSPs offer the industry's highest level of performanceto address the demands of the digital age. At clock rates of up to 1 GHz, C64x DSPs can process information at rates up to 8000 MIPS with costs as low as $19.95. In addition to a high clock rate, C64x DSPs can do more work each cycle with built-in extensions.These extensions include new instructions to accelerate performance in key application areas such as digital communications infrastructure and video and image processing. C67x:For designers of high-precision applications, C67x floating-point DSPs offer the speed, precision, power savings and dynamic range to meet a wide variety of design needs. These dynamic DSPs are the ideal solution for demanding applications like audio, medical imaging, instrumentation and automotive. A.A.2009-10

  4. A.A.2009-10 Architectural Overview TMS320C6000 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004

  5. N • anxn Y = * n = 1 Prodotto Scalare tra due vettori TMS320 C6xx DSP System Block Diagram Instruction Set A.A.2009-10

  6. Scalar Product of Vectors N • anxn Y = * n = 1 = a1* x1 + a2 * x2+... + aN *xN Two basic Operations are required for this algorithm. -Multiplication -Addition Therefore two basic Instructions are required TMS320 C6xx SOP Algorithm It has been shown in Introduction that SOP is the key element for most DSP algorithms. The implementation in this module will be done inassembly for C6xx A.A.2009-10

  7. N • anxn Y = * n = 1 Multiply (MPY) = a1* x1 + a2 * x2+... + aN *xN The multiplication of a1 by x1 is done in assembly by the following instruction: MPY a1, x1, Y This instruction is performed by a multiplier unit that is called “.M” A.A.2009-10

  8. 40 • an xn Y = * n = 1 Multiply (.M unit) .M The .M unit performs multiplications in hardware MPY.Ma1, x1, Y Note: 16-bit by 16-bit multiplier provides a 32-bit result. 32-bit by 32-bit multiplier provides a 64-bit result. A.A.2009-10

  9. 40 • an xn Y = * n = 1 Addition(.L unit) MPY .M a1, x1, prod ADD.LY, prod, Y .M .L RISC processors such as the C6000 use registers to hold the operands, so lets change this code. A.A.2009-10

  10. 40 • an xn Y = * n = 1 Register File A A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... ... 32-bits Register FileA MPY .M a1, x1, prod ADD .L Y, prod, Y MPY .M A0, A1, A3 ADD .L A4, A3, A4 Let us correct this by replacing a, x, prod and Y by the registers as shown above. A.A.2009-10

  11. Register File A A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... ... 32-bits Specifying Register Names Register File A contains 16 registers (A0 -A15) which are 32-bits wide. A.A.2009-10

  12. .D Data Memory Data loading (load unit .D) Register File A Q: How do we load the operands into the registers? A0 A1 A2 A3 A4 A15 a1 .M x1 A: The operands are loaded into the registers by loading them from the memory using the .D unit. prod .L Y ... ... It is worth noting at this stage that the only way to access memory is through the .D unit. 32-bits A.A.2009-10

  13. .D Data Memory Load Instruction Register File A Q: Which instruction(s) can be used for loading operands from the memory to the registers? A0 A1 A2 A3 A4 A15 a1 .M x1 prod .L Y ... ... 32-bits A.A.2009-10

  14. .D Data Memory Load Instructions Register File A Q: Which instruction(s) can be used for loading operands from the memory to the registers? A0 A1 A2 A3 A4 A15 a1 .M x1 prod A: The load instructions. .L Y LDB, LDHLDW,LDDW ... ... 32-bits A.A.2009-10

  15. Data 32 bits address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits Using the Load Instructions Byte Before using the load unit you have to be aware that this processor is byte addressable, which means that each byte is represented by a unique address. Also theaddresses are 32-bit wide. A.A.2009-10

  16. Data address 00000000 a1 00000002 x1 00000004 prod 00000006 00000008 Y FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: Where: Rn is a register that contains the address of the operand to be loaded and Rm is the destination register. LD *Rn,Rm A.A.2009-10

  17. Data address 00000000 a1 00000002 x1 00000004 prod 00000006 00000008 Y FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: The question now is how many bytes are going to be loaded into the destination register? LD *Rn,Rm A.A.2009-10

  18. Data address The syntax for the load instruction is: 00000000 a1 LD *Rn,Rm 00000002 x1 00000004 prod 00000006 00000008 Y FFFFFFFF 16-bits Using the Load Instructions • The answer, is that it depends on the instruction you choose: • LDB: loads one byte(8-bit) • LDH: loads half word(16-bit) • LDW: loads a word(32-bit) • LDDW: loads a double word(64-bit) • Note: LD on its own does not exist. A.A.2009-10

  19. Data address 1 0 The syntax for the load instruction is: 0xA 0xB 00000000 0xC 0xD 00000002 LD *Rn,Rm 0x02 0x01 00000004 0x04 0x03 00000006 0x06 0x05 00000008 0x08 0x07 FFFFFFFF 16-bits Using the Load Instructions • Example: • If we assume that A5 = 0x4 then: • LDB *A5, A7 ; • gives A7 = 0x00000001 • LDH *A5,A7; • gives A7 = 0x00000201 • LDW *A5,A7; • gives A7 = 0x04030201 • LDDW *A5,A7:A6; • gives A7:A6 = 0x0807060504030201 Little Endian la parte meno significativa va memorizzata per prima, all'indirizzo più basso di memoria A.A.2009-10

  20. Data address 1 0 The syntax for the load instruction is: 0xA 0xB 00000000 0xC 0xD 00000002 LD *Rn,Rm 0x2 0x1 00000004 0x4 0x3 00000006 0x6 0x5 00000008 0x8 0x7 FFFFFFFF 16-bits Using the Load Instructions Q: If data can only be accessed by the load instruction and the .D unit, how can we load the register pointer Rn in the first place? A.A.2009-10

  21. Loading the Pointer*Rn • The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL .? a, A5 (‘a’ is a constant or label) • How many bits represent a full address? 32 bits • So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode). A.A.2009-10

  22. ah al a ah x A5 Loading the Pointer*Rn • To solve this problem another instruction is available: MVKH eg.MVKH .? a, A5 (‘a’ is a constant or label) • Finally, to move the 32-bit address to a register we can use: MVKL a, A5 MVKH a, A5 A.A.2009-10

  23. Loading the Pointer*Rn • Always use MVKL then MVKH, look at the following examples: Example 1 (A5 = 0x87654321) MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC (sign extension) MVKH 0x1234FABC, A5 A5 = 0x1234FABC OK Example 2 (A5 = 0x87654321) MVKH 0x1234FABC, A5 A5 = 0x12344321 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC Wrong A.A.2009-10

  24. MVKLpt1, A5 MVKHpt1, A5 MVKLpt2, A6 MVKHpt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 .D Data Memory LDH, MVKL and MVKH IPOTESI Register File A Le componenti aie xi sono numeri interi da 16 bits A0 A1 A2 A3 A4 A15 a1 .M x1 prod .L Y ... ... pt1 and pt2 point to some locations in the data memory. 32-bits A.A.2009-10

  25. Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1* x1 So let’s create a loop so that we can implement the SOP for N Taps. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 A.A.2009-10

  26. Creating a loop –B instruction So far we have only implemented the SOP for one tap only, i.e. Y= a1* x1 So let’s create a loop so that we can implement the SOP for N Taps. With the C6000 processors there are no dedicated instructions such as block repeat. The loop is created using the Binstruction. A.A.2009-10

  27. What are the steps for creating a loop ? • Create a label to branch to. • Add a branch instruction, B. • Create a loop counter (LC). • Add an instruction to decrement the LC. • Make the branch conditionalbased on LC. A.A.2009-10

  28. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 1. Create a label to branch to A.A.2009-10

  29. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop 2. Add a branch instruction, B. A.A.2009-10

  30. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop Register File A A0 A1 A2 A3 A15 a Register File A x .S A0 A1 A2 A3 A15 a .M x prod Y .M prod .L Y ... .L ... .D .D 32-bits 32-bits Data Memory Which unit is used by the B instruction? A.A.2009-10

  31. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 MVKL .S count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop Register File A A0 A1 A2 A3 A15 a Register File A x .S A0 A1 A2 A3 A15 a .M x prod Y .M prod .L Y ... .L ... .D .D 32-bits 32-bits Data Memory 3. Create a loop counter. B registers will be introduced later A.A.2009-10

  32. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 MVKL .S count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Register File A A0 A1 A2 A3 A15 a Register File A x .S A0 A1 A2 A3 A15 a .M x prod Y .M prod .L Y ... .L ... .D .D 32-bits 32-bits Data Memory 4. Decrement the loop counter A.A.2009-10

  33. 5. Make the branch conditional based on the value in the loop counter • What is the syntax for making instruction conditional? [condition] Instruction Label e.g. [B1] B loop (1) The condition can be one of the following registers: A1, A2, B0, B1, B2. (2) Any instruction can be conditional. A.A.2009-10

  34. 5. Make the branch conditional based on the value in the loop counter • The condition can be inverted by adding the exclamation symbol “!” as follows: [!condition] Instruction Label e.g. [!B0] B loop; branch if B0= 0 [B0] B loop; branch if B0!= 0 A.A.2009-10

  35. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop Register File A A0 A1 A2 A3 A15 a Register File A x .S A0 A1 A2 A3 A15 a .M x prod Y .M prod .L Y ... .L ... .D .D 32-bits 32-bits Data Memory 5. Make the branch conditional A.A.2009-10

  36. 32-bit B 21-bitrelative address More on the Branch Instruction (1) • With this processor all the instructions are encoded in a 32-bit. • Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. • Case 1: B.S1label • Relative branch. • Label limited to +/- 220 offset. A.A.2009-10

  37. 32-bit B 5-bit register code More on the Branch Instruction (2) • By specifying a register as an operandinstead of a label, it is possible to have an absolute branch. • This will allow a dynamic range of 232. • Case 2: B .S2register • Absolute branch. • Operates on .S2 ONLY! A.A.2009-10

  38. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop Testing the code This code performs the following operations: a0*x0 + a0*x0 + a0*x0 + … + a0*x0 However, we would like to perform: a0*x0 + a1*x1 + a2*x2 + … + aN*xN A.A.2009-10

  39. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop Modifying the pointers The solution is to modify the pointers A5 and A6 A.A.2009-10

  40. Indexing Pointers Description Syntax PointerModified *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement No No No Yes Yes Yes Yes • [disp] specifies # elements - size in DW, W, H, or B. • disp = R or 5-bit constant. • R can be any register. A.A.2009-10

  41. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loopLDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop Modify and testing the code This code now performs the following operations: a0*x0 + a1*x1 + a2*x2 + ... + aN*xN A.A.2009-10

  42. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop STH .D A4, *A7 Store the final result This code now performs the following operations: a0*x0 + a1*x1 + a2*x2 + ... + aN*xN A.A.2009-10

  43. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop STH .D A4, *A7 Store the final result The Pointer A7 is now initialised. A.A.2009-10

  44. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 ZERO .L A4 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop STH .D A4, *A7 What is the initial value of A4? A4 is used as an accumulator, so it needs to be reset to zero. A.A.2009-10

  45. TMS320 C6xx Codex Complete *A5 = an (16 bits) A0 MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 N, B0 ZERO .L1 A4 loop LDH .D1 *A5++, A0 LDH .D1 *A6++, A1 MPY .M1 A0, A1, A3 ADD .L1 A4, A3, A4 SUB .S2 B0, 1, B0 [B0] B .S1 loop STH .D1 A4, *A7 *A7 = Y (16 bits) A4 *A6 = xn (16 bits) A1 32 bits 32 bits 32 bits 16 bits (pt3) (pt1) (pt2) 16 bits 16 bits 16 bits B0 = N (16 bits) A.A.2009-10

  46. 40 • an xn Y = * n = 1 Note: Assume that A4 was previously cleared and the pointers are initialised. Assume thatA2 is B0 Code Review(using side A only) MVK .S1 40, A2; A2 = 40, loop count loop: LDH .D1 *A5++, A0 ; A0 = a(n) LDH .D1 *A6++, A1 ; A1 = x(n) MPY .M1 A0, A1, A3 ; A3 = a(n) * x(n) ADD .L1 A4, A3, A4 ; Y = Y + A3 SUB .L1 A2, 1, A2 ; decrement loop count [A2] B .S1 loop ; if A2  0, branch STH .D1 A4, *A7 ; *A7 = Y A.A.2009-10

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