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Electronic Testing Education, Research and Training Infrastructure

Electronic Testing Education, Research and Training Infrastructure. NSF Computing Research Infrastructure (CRI) Project at Auburn University Vishwani Agrawal vagrawal@eng.auburn.edu. A Test Lab Infrastructure Project. Objective: Establish a modern VLSI test Lab at Auburn for

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Electronic Testing Education, Research and Training Infrastructure

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  1. Electronic Testing Education,Research and Training Infrastructure NSF Computing Research Infrastructure (CRI) Project at Auburn University Vishwani Agrawal vagrawal@eng.auburn.edu

  2. A Test Lab Infrastructure Project • Objective: Establish a modern VLSI test Lab at Auburn for • Teaching – Include testing in university courses. • Research – Conduct leading-edge research. • Training – Develop training facilities for industry. • Collaborators: Auburn (5), Alabama-Tuscaloosa (1), Alabama-Huntsville (1), Tuskegee (2). • Funding: NSF, $1.1M ($600k, Auburn), Oct/07 – Sep/10.

  3. Principal Investigators • Auburn University • Vishwani Agrawal • Foster Dai • Vic Nelson • Adit Singh • Chuck Stroud • University of Alabama in Huntsville • Rhonda Gaede • University of Alabama Tuscaloosa • Bruce Kim • Tuskegee University • HiraNarang • Muhammad Ali • Chung-Han Chen

  4. Proposed Tasks • VLSI test laboratory at Auburn. To be established in collaboration with the three other universities. The facility will be available to remote users via networking. • Test lab applications. Applications for inclusion in university curricula. These will include experiments on testing of digital, analog and RF chips, FPGAs and system-on-chip devices, and on methods for assessing yield and reliability of devices. • Training Classes. Industry-oriented training with hands-on test lab exercises. • Research. Silicon debug methods, ATE-based formal verification, mixed-signal and RF circuit testing, SOC testing, FPGA testing, and non-redundant and parallel architectures for improving yield and reliability. Develop Silicon benchmarks, circuits with fault-injection capabilities, that will be made available to researchers working on debug methods.

  5. Vision of the Project

  6. Subtask – Infrastructure Matrix

  7. Project Status – January 2009 • Proposal submitted in November 2006. • Proposal revised in August 2007. • Awarded October 2007. • Year 1 progress report submitted and approved in August 2008. • Order placed for T2000GS in September 2009 • Year 2 plan: • ATE installed and running (Delivery expected in Feb 2009) • Develop classroom experiments on digital test

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