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Synchronization over packet-switching networks: theory and applications

Synchronization over packet-switching networks: theory and applications. Raffaele Noro PhD exam Lausanne, May 12 th 2000. Outline. Synchronization over packet-switching networks: Needs and problems in packet-switching networks Theory: Conventional solution: Phase-Locked Loops (PLLs)

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Synchronization over packet-switching networks: theory and applications

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  1. Synchronization overpacket-switching networks:theory and applications Raffaele Noro PhD exam Lausanne, May 12th 2000

  2. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  3. Synchronous Time Division Multiplexing Periodic, fixed-size frames Global, static synchronization Asynchronous Statistical Multiplexing Bursty traffic, variable delay Point-2-point, dynamic synchronization Synchronization over packet-switching networks • Voice • Digital TV • … • Voice • Digital TV • … Synchronous application Synchronous application Synchronous application Synchronous application Application-specific synchronization Global to pt2pt synchronization Circuit-switching network Packet-switching network • Requirement of point-to-point synchronization: • Synchronize the terminal clocks (fast, efficiently) even in the presence of (higher) transmission jitter • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  4. The problem of synchronization in packet-switching networks - part I Variable delay [Dmin…Dmax] Constant delay • Network jitter • Removed through the de-jittering buffer • Controlled playout of data • Optimal size: B= (Dmax- Dmin)· C Packet-switching network Generation Playout de-jittering buffer • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  5. The problem of synchronization in packet-switching networks - part II Variable delay [Dmin…Dmax] Constant delay • Physically dispersed clocks • Clock drift Df /f : speed of writing  speed of reading (on average) • Overflow (or underflow) of the de-jittering buffer • Time-to-overflow (or underflow) depends on buffer size, bitrate, and drift Packet-switching network Generation Playout de-jittering buffer The Network Time Protocol (NTP, [Mills ’92]) provides only poor clock synchronization guarantees (millisecond accuracy at best) Example: B= 10 kbits, C= 1 Mbps, Df/f= 10-4 (10 ms of jitter absorption in the buffer) T= 100 seconds !! • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  6. The problem of synchronization in packet-switching networks Variable delay [Dmin…Dmax] Constant delay • Objective Control and reduce to zero the clock drift within a convergence time shorter than the time-to-overflow: D f /f  0 within t < T Packet-switching network Generation Playout de-jittering buffer • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  7. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  8. Synchronization of dispersed clocks Packet-switching network Generation Playout • Timestamping of data flow • Information about the timing of data • Information about the transmitter clock • Processing of timestamps • Jitter limits the ability of the algorithm to reduce Df /f to zero • A convergence time is needed (… still not exceeding T ) Synch algorithm Synchonized clock Clock of transmitter Clock of receiver (free-running) Timestamps Timing of transm. data Timing of receiv.+ jitter data Effect of jitter and drift cTx(t) cRx(t) Timing of transm. (original) cTx(t) • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  9. State of the art: Phase-Locked Loops (PLLs) PLL synchronization algorithm Jitter Reference clock signal PLL Local clock Synchronized clock signal Control signal Periodic pulses Phase comparator xi cRxPLL(t) Loop filter VCO (pulse generator) Pulse counter + - • Linear filtering of network jitter • Proportional-Integrative (PI) loop filter • Controlled frequency of the local oscillator (VCO) • Feedback used to trigger an error signal • Characteristics of linear filtering • For better accuracy  narrower bandwidth • With narrower bandwidth  longer response time Error signal • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  10. State of the art: Phase-Locked Loops (PLLs) PLL synchronization algorithm Jitter Reference clock signal PLL Local clock Synchronized clock signal Control signal Periodic pulses Phase comparator xi cRxPLL(t) Loop filter VCO (pulse generator) Pulse counter + - • Accuracy • Performance budget Error signal Relative frequency drift, Kp= 0.0015, Ki= 0.000005 0.02 Network jitter 0.01 Residual jitter Frequency drift (%) 0 -0.01 The performance budget of PLLs (here: 0.005) results below the expected performance budget for packet-switching (ex: 0.2) Convergence time -0.02 2000 4000 6000 8000 10000 Time (s) • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  11. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  12. Least-square Linear Regression (LLR): statistical filtering of network jitter Clock model: cTx(t)= a cRx(t)+ b [Mills, ’93; Cristian ‘89] y(t)= CTx(t) xN, yN Estimation of (a, b) with the N last collected (x, y) x1, y1 x(t)= CRx(t) Each cycle is triggered by the reception of one timestamp Recovered clock: cTxLLR(t)= aLLR cRx(t)+ bLLR • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  13. LLR circuitry and performance budget Slope computation Syi Low-pass filter yi + aLLR ^2 - - Mem. âLLR + + Syi2  x(1- a) + xN - ^2 Mem. xa - Sxiyi x Mem. + cTxLLR(t) xN • Accuracy d0  20 • Performance budget F  0.2 + + - - Sxi Mem. + x - + x xi Timekeeping cRx(t) Relative frequency drift, N= 1000, a= 0.98 0.02 Network jitter 0.01 Residual jitter Frequency drift (%) 0 • The performance budget of LLR (here: 0.2) is • Better than for PLLs (10 to 100 times) • Supports the needs of packet-switching • applications -0.01 Convergence time -0.02 2000 4000 6000 8000 10000 Time (s) • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  14. Comparative perfomance of LLR and PLL Accuracy (jitter resilience capability) 0% 90% 99% 99.9% 10 Region of interest for packet-switching networks • Choose the parameters of LLR (N, a), and of PLL (Kp, Ki)  trade-off between accuracy and rapidity • The trade-off is much better with the LLR 100 LLR: Accuracy/ Conv.time  0.25 / t (t= 0.1 s for this example) 1000 PLL: Accuracy/ Conv.time  0.05 (nearly independent of t) 10000 Convergence time (s) • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  15. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  16. Applications and synchronization (I):Circuit Emulation over IP networks Objective • Support of circuit-switched leased-lines (e.g., T1) with high-speed IP backbones (e.g., optical IP) [ TDM-over-IP Forum, Geneva ‘99] Relevance • Seamless migration to IP backbones without interruption of legacy services • Transparent to the end-user • Can be simpler than VoIP solutions Contributions • Definition of the functions • Design of the protocol • Performance assessment • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  17. IP Applications and synchronization (I):Circuit Emulation over IP – definition of the functions User (e.g., T1/T3 leased lines) IP Network operator • Emulation functions are allocated in a Circuit Emulation adapter • Circuit Emulation • Adapter • Jitter Removal • Clock recovery • Data structure • handling IP backbone • TDM traffic • Isochronous • Periodic • IP packets • Asynchronous • Aperiodic Circuit Emulation Adapter TDM Circuit Emulation LT IP LT f • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  18. Applications and synchronization (I):Circuit Emulation over IP – design of the protocol • Real-Time Protocol has been developed for real-time applications, including VoIP applications [Schulzrinne, ’96] • Native features include timestamping and sequencing • Includes a control protocol – RTCP • Extended features can be added Timestamping & Sequencing RTP UDP RTP-H Payload IP UDP-H RTP-H Payload IP-H UDP-H RTP-H Payload • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  19. Applications and synchronization (I):Circuit Emulation over IP – design of the protocol RTP packet RTCP message PX V M CC PT sequence number Other fields • Data timing, jitter removal timestamp • Clock recovery source clock indication • Data handling structure and spacing • Session information RTCP messages timestamp Fixed header d_max x synchronization source (SSRC) id. SR extension or APP data structure spacing contributing source (CSRC) id. #1 … ... number unused profile length Extension header source clock indication (optional) Payload of Consecutive Data Units Payload 4 bytes • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  20. Applications and synchronization (I):Circuit Emulation over IP – design of the adapter Circuit Emulation adapter Circuit Emulation adapter non-idle idle Transmitter part RTP packets Receiver part payload Packing Timestamps + Source clock indications Timestamp Scheduling Source clock indications Structure Spacing Leased line Leased line Master clock Slave clock (LLR/PLL) Structure Spacing RTP packets Scheduling Timestamp Timestamp Packing payload Transmitter part Receiver part • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  21. Same nominal convergence time, more stable end-to-end delay with LLR (and more stable bitrate) Applications and synchronization (I):Circuit Emulation over IP – performance assessment End-to-end delay and loss rate for: • Best-effort service class • Expedited forwarding service class • Guaranteed service Network jitter model: [Bolot, ‘93] End-to-end delay for a LLR with N= 1200 and a= 0.992 End-to-end delay for a PLL with Kp= 0.05 and Ki= .0005 220 220 200 Best Effort 200 Best Effort 180 180 160 Convergence time= 100 s 160 Convergence time= 100 s 140 Delay (ms) Delay (ms) 140 120 120 100 Exp. Forwarding 100 Exp. Forwarding 80 Guar. Service 80 Guar. Service 60 60 0 50 100 150 0 50 100 150 Time (s) Time (s) • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  22. 0 10 -1 10 Guar. Service Loss rate -2 10 Exp. Forwarding Loss rate (log scale) for a LLR with N= 1200 and a= 0.992 -3 0 10 Best Effort 10 -1 -4 10 Guar. Service 10 0 50 100 150 Time (s) Loss rate -2 10 Exp. Forwarding -3 10 Best Effort Same nominal convergence time, lower losses with LLR -4 10 0 50 100 150 Time (s) Applications and synchronization (I):Circuit Emulation over IP – performance assessment Loss rate (log scale) for a PLL with Kp= 0.05 and Ki= .0005 • Introduction • Theory • Applications — Application I: Circuit Emulation • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  23. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  24. Applications and synchronization (II)Synchronous AAL Objective • Tranport of statistically multiplexed Variable Bitrate (VBR) traffic in ATM networks with constant end-to-end delay [AAL-1; AAL-2; AAL-3/4; AAL-5] Relevance • Multimedia applications (Voice over ATM, video distribution) Contributions • Design of the protocol • Performance assessment Constant delay Application Application Synch AAL Variable delay ATM layer Synch AAL ATM layer ATM switch ATM switch • Introduction • Theory • Applications — Application II: Synchronous AAL • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  25. Applications and synchronization (II)Synchronous AAL – design of the protocol Application layer Synchronous AAL SDU 4-byte timestamp added by the synchronous AAL (in units of microseconds) SSCS TS (AAL-5) CPCS SDU Reserved CRC Synchronous AAL CPCS (AAL-5) TS (AAL-5) CPCS PDU Padding Length SAR (AAL-5) ATM layer • Introduction • Theory • Applications — Application II: Synchronous AAL • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  26. Applications and synchronization (II)Synchronous AAL – design of the protocol Synchronous AAL (transmitter) Synchronous AAL (receiver) AAL SDU AAL SDU Scheduling Timestamp Transmitter clock Self-synch LLR/PLL Timestamp AAL SDU SSCS SSCS AAL-5 CPCS trailer AAL-5 CPCS trailer AAL-5 CPCS SDU AAL-5 CPCS SDU CPCS CPCS SAR SAR ATM cells payload ATM cells payload From the ATM network To the ATM network • Introduction • Theory • Applications — Application II: Synchronous AAL • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  27. Loss rate (log scale) for a PLL with Kp= 0.05 and Ki= 0.00025 -1 10 Same nominal convergence time, lower loss with LLR during the convergence time -2 10 Loss rate Loss rate (log scale) for a LLR with N= 10000 and a= 0.9992 -1 10 -3 10 -2 10 -4 10 0 50 100 150 200 250 Time (s) Loss rate -3 10 -4 10 0 50 100 150 200 250 Time (s) Applications and synchronization (II)Synchronous AAL – performance assessment Loss rate and rate discrepancy for: • 376-byte AAL SDU • 1 Mbps average rate • Erlang jitter distribution Network jitter model:[Parekh, ’93; Singh, ’94; …] Convergence time= 100 s Convergence time= 100 s • Introduction • Theory • Applications — Application II: Synchronous AAL • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  28. Difference between output and inputrate per each second of the session (PLL) 20 15 Average rate= 1 Mbps 10 Convergence time= 100 s 5 Difference of rate (kbps) 0 -5 -10 -15 -20 0 50 100 150 200 250 Time (s) Applications and synchronization (II)Synchronous AAL – performance assessment Difference between output and input rate per each second of the session (LLR) 20 15 10 Average rate= 1 Mbps Convergence time= 100 s 5 Difference of rate (kbps) 0 -5 -10 -15 -20 0 50 100 150 200 250 Time (s) Same nominal convergence time, more stable rate with LLR during the convergence time • Introduction • Theory • Applications — Application II: Synchronous AAL • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  29. Outline • Synchronization over packet-switching networks: • Needs and problems in packet-switching networks • Theory: • Conventional solution: Phase-Locked Loops (PLLs) Do not scale to packet-switching networks • Proposed solution: Least-square Linear Regression (LLR) Satisfies the new requirements • Applications: • Circuit Emulation over IP Networks • Synchronous ATM Adaptation Layer (AAL) • Digital TV over packet-switching networks • Conclusions • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  30. Applications and synchronization (III)Digital TV services Objective • Synchronization of MPEG-2 systems over IP and ATM channels [MPEG-2, ’94; Tryfonas ’99; …] Relevance • Penetration of Digital TV services • Network-independence of MPEG codecs Contribution • Performance assessment The electron beam of TV must be in-sync with the video camera Residential user Stored material (films) Receiver/ decoder #1 Return channel Live material (TV) Video server DVD Distribution network The decoder must synchronize to the server: - generation of TV signal - audio and video sync • DVB: Video broadcast (cable, terrestrial and sat) • VoD: Video-on-demand (interactive TV) • PPV: Pay-per-view (pre-scheduled TV programs) Receiver/ decoder #N • Introduction • Theory • Applications — Application III: Digital TV services • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  31. Applications and synchronization (III)Digital TV services– standardized protocol Timestamping for: • Intra- and inter-flow synchronization (DTS or PTS) • Clock recovery and synchronization (PCR) Audio and video part contain Presentation TS referred to a common timebase Audio Video Audio Video Compression PTS/DTS PTS/DTS Decompression Program clock Program clock PES packetizer PES depacketizer PCR Synch LLR/PLL Mux Demux Transmitter Receiver Transport network The PC Reference is used to reconstruct the common timebase PCR PCR • Introduction • Theory • Applications — Application III: Digital TV services • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  32. Same nominal accuracy, faster convergence with LLR Applications and synchronization (III)Digital TV services – performance assessment Frequency reconstruction error of the System Clock • 50 ms of network jitter • PCRs inserted each 100 ms • 20 parts-per-million (tolerance dictated by MPEG-2) Network jitter model: [Andreotti, ’95; Noro, ’99; …] Frequency error (log scale) of the recovered clock with N=4000 and a=0.99 Frequency error (log scale) of the recovered clock with Kp= 0.002, Ki= 0.000001 1000 1000 Convergence time= 70 s Convergence time= 2000 s 100 100 10 10 Frequency deviation (parts-per-million) 1 Frequency deviation (parts-per-million) 1 0.1 0.1 0.01 0.01 1000 2000 3000 4000 5000 1000 2000 3000 4000 5000 Time (s) Time (s) • Introduction • Theory • Applications — Application III: Digital TV services • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  33. Conclusions Addressed problem • How to synchronize fast and efficiently dispersed clocks in the presence of network jitter – satisfy new needs of packet-switching Contributions • A solution based on LLR– overcomes limitations of conventional PLLs • Circuit Emulation over IP – support to legacy TDM leased-lines • Synchronous AAL – transport of ATM traffic with constant delay • Digital TV over packet-switching – distribution of MPEG-2 streams Future work • Standardization of Circuit Emulation in the Internet community (RFCs) • Synchronization for mobile services • Global synchronization for IP networks • Introduction • Theory • Applications • Conclusions Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

  34. Most relevant publications Patents • ''Real-time remote inspection of high resolution images'', European Patent n.EP946919A1, Issued Oct. 1999 • R. Noro, J.P. Hubaux and M. Hamdi, ``Clock Synchronization over Data Transmission Networks'', US Patent Application, filed July 1998, in progress • M. Hamdi, R. Noro and J.P. Hubaux, ``Fresh Packet First Scheduling for Voice Traffic in Congested Networks'', US Patent Application, filed July 1998, in progress Articles • ''Circuit Emulation over IP Networks'', Proc. of the IFIP 6th International Workshop on Protocols for High-Speed Networks, Salem- MA, USA, Aug. 1999 • ''Clock Synchronization of MPEG-2 Services over Packet Networks'', Telecommunication Systems Journal, Baltzer Science Publisher, Vol. 11, Nos. 1- 2, Mar. 1999, • ''Improving Clock Synchronization for MPEG-2 Services over ATM Networks'', Proc. of the 4th Int. Workshop on Interactive Distributed Multimedia Systems, Darmstadt, Germany, Sep. 1997, pp. 176- 188 Seminars • Design of a Circuit Emulation Protocol based on extended functionalities of RTP, at the TDM over IP Forum, Geneva, Switzerland, Oct. 1999 • Synchronization of Networks and Applications: a Survey, EPFL-SSC Seminars Series, Lausanne, Switzerland, July 1999 Synchronization over packet-switching networks: theory and applications Raffaele Noro, PhD exam, May 12th 2000

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