Virtual Memory Part 1 Li-Shiuan Peh Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Techn

1. Virtual Memory Part 1 Li-Shiuan Peh Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology http://csg.csail.mit.edu/6.S078

2. Virtual Memory Basics Physical Memory (Caches, DRAM) Address Mapping ISA machine language address virtual address physical address lw$t0, 32($s3) 0xABCDEFGH 01HGFEDCB 32-bit ISA 1GB DRAM (230) lw$t0, 32($s3) 0xABCDEFGHIJKLMNOP 0xHGFEDCBA 32-bit ISA 4GB DRAM (232) lw$t0, 32($s3) 0xABCDEFGHIJKLMNOP 0xIHGFEDCBA 64-bit ISA 64GB DRAM (236) http://csg.csail.mit.edu/6.S078

3. Virtual Memory Basics: Pages Physical Memory Address Mapping ISA machine language address virtual address physical address lw$t0, 32($s3) 0xABCDEFGH 0xHGFEDFGH Mapping individual addresses incurs too much overhead: Let’s page it: Chunk address space! Physical Memory Address Mapping (Page Tables) ISA machine language address virtual address physical address lw$t0, 32($s3) Page Index:0xABCDE 0xHGFED Page Offset:0xFGH0xFGH http://csg.csail.mit.edu/6.S078

4. page number offset 1 0 3 2 Paged Memory Systems • Processor generated address can be interpreted as a pair <page number, offset> • A page table contains the physical address of the base of each page 0 0 1 1 2 2 3 3 Address Space of User-1 Page Table of User-1 Page tables make it possible to access and store pages of a program non-contiguously http://csg.csail.mit.edu/6.S078

5. Why Virtual Memory?Illusion of a large, private, uniform store OS • Protection & Privacy • several users, each with their private address space and one or more shared address spaces • page table  name space • Demand Paging • Provides the ability to run programs larger than the primary memory • Hides differences in machine configurations • The price is address translation on • each memory reference useri Swapping Store Primary Memory mapping VA PA PageTbl http://csg.csail.mit.edu/6.S078

6. OS pages User 1 VA1 Physical Memory Page Table User 2 VA1 Page Table VA1 User 3 Page Table free Why Virtual Memory:Reason #1: Protection & PrivacySo: Private Address Space per User • Each user has a page table • Page table contains an entry for each user page http://csg.csail.mit.edu/6.S078

7. Protection Check Address Translation & Protection Virtual Address Virtual Page No. (VPN) offset Kernel/User Mode Read/Write Address Translation Exception? Physical Address Physical Page No. (PPN) offset Every instruction access and data access needs address translation and protection checks http://csg.csail.mit.edu/6.S078

8. CPU Why Virtual Memory:Reason #2: Demand Paging (VM >> PM)So: Page Table keeps track of disk vs. DRAM PhysicalMemory (DRAM) 0: 1: Page Table Virtual Addresses Physical Addresses 0: 1: Store 0x10 Load 0xf0 P-1: N-1: Disk Page Faults: Page not in DRAM, so, load from Disk to DRAM!

9. VPN Offset Data Pages Data word Linear Page Table: Implementing Demand Paging and Protection Page Table PPN • Page Table Entry (PTE) contains: • A bit to indicate if a page exists • PPN (physical page number) for a memory-resident page • DPN (disk page number) for a page on the disk • Status bits for protection and usage • OS sets the Page Table Base Register whenever active user process changes PPN DPN PPN Offset DPN PPN PPN DPN DPN VPN DPN PPN PPN PT Base Register Virtual address http://csg.csail.mit.edu/6.S078

10. PT User 1 VA1 PT User 2 User 1 VA1 User 2 Page Tables in Physical Memory:1 memory access for translation +1 memory access for actual access! +? translation access Idea: cache the address translation of frequently used pages – Translation Look-aside Buffer (TLB) http://csg.csail.mit.edu/6.S078

11. A cache for address translations:Translation LookasideBuffers (TLB) Cache address translations in TLB TLB hit  Single Cycle Translation TLB miss  Page Table Walk to find Page Table Entry in DRAM, and refill into TLB virtual address VPN offset V R W D tag PPN hit? physical address PPN offset http://csg.csail.mit.edu/6.S078

12. Virtual Memory: Translation + Access Physical Memory (Caches, DRAM) Address Mapping ISA machine language address virtual address physical address Physical Memory handles the access from DRAM Virtual Memoryhandles thetranslation and filling DRAM from Disk http://csg.csail.mit.edu/6.S078

13. Virtual Memory:putting it all together Virtual Address hardware hardware or software software TLB Lookup miss hit Page Table Walk (DRAM) Protection Check Translation miss! the page is Ïmemory Îmemory denied permitted Protection Fault Page Fault (OS loads page) Accessmiss! Physical Address (to cachehierarchy) Update TLB Where? SEGFAULT http://csg.csail.mit.edu/6.S078

14. Handling a TLB Miss • Software (MIPS, Alpha) • TLB miss causes an exception and the operating system walks the page tables and reloads TLB. Aprivileged “untranslated” addressing mode used for walk • Hardware (SPARC v8, x86, PowerPC) • A memory management unit (MMU) walks the page tables and reloads the TLB http://csg.csail.mit.edu/6.S078

15. Page Fault Handler • When the referenced page is not in DRAM: • The missing page is located (or created) • It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk • If no free pages are left, a page is swapped out approximate LRU replacement policy • Since it takes a long time (msecs) to transfer a page, page faults are handled completely in software (OS) • Untranslated addressing mode is essential to allow kernel to access page tables http://csg.csail.mit.edu/6.S078

16. PC D E M W Virtual memory + processor + caches Inst TLB Inst. Cache Decode Data TLB Data Cache + TLB miss? Page Fault? Protection violation? TLB miss? Page Fault? Protection violation? http://csg.csail.mit.edu/6.S078

17. PA VA Physical Cache Primary Memory CPU TLB Physical or Virtual Address Caches? • one-step process in case of a hit (+) • cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) • aliasing problems due to the sharing of pages (-) Alternative: place the cache before the TLB VA Primary Memory (StrongARM) PA Virtual Cache CPU TLB http://csg.csail.mit.edu/6.S078

18. Aliasing in Virtual-Address Caches Page Table Tag Data VA1 1st Copy of Data at PA VA1 Data Pages VA2 2nd Copy of Data at PA PA VA2 Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! Two virtual pages share one physical page • General Solution: Disallow aliases to coexist in cache • Software (i.e., OS) solution for direct-mapped cache • VAs of shared pages must agree in cache index bits • Hardware solution for direct-mapped cache • Cache size < Page size http://csg.csail.mit.edu/6.S078

19. Let’s build! Fetch Decode RegRead Execute Memory Write-back pc F D R X M W fr dr rr xr mr VA VA VirtualI$ VirtualD$ I$ miss (VA) D$ miss (VA) TLB PA TLB miss PhysicalL2$ Page Table Walker Page Fault DRAM (Page Table) Page Fault Exception DRAM (Pages) http://csg.csail.mit.edu/6.S078