Experiment 7 VHDL Modeling of Embedded Microprocessors and Microcontrollers

1. Experiment 7VHDL Modeling of Embedded Microprocessors and Microcontrollers ECE 448 – FPGA and ASIC Design with VHDL

2. Simple Microprocessor ECE 448 – FPGA and ASIC Design with VHDL

3. Basic Architecture Processor Control unit Datapath ALU Controller Control /Status Registers PC IR I/O Memory • Control unit and datapath • Note similarity to single-purpose processor • Key differences • Datapath is general • Control unit doesn’t store the algorithm – the algorithm is “programmed” into the memory Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction" ECE 448 – FPGA and ASIC Design with VHDL

4. Instruction Cycles Processor Fetch ops Store results Control unit Datapath Fetch Decode Exec. ALU Controller Control /Status Registers 10 PC IR R0 R1 load R0, M[500] I/O ... Memory 100 load R0, M[500] 500 10 101 inc R1, R0 501 ... 102 store M[501], R1 PC=100 clk 100 ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

5. Architectural Considerations Processor Control unit Datapath ALU Controller Control /Status Registers PC IR I/O Memory • Clock frequency • Inverse of clock period • Must be longer than longest register to register delay in entire processor • Memory access is often the longest ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

6. A Simple (Trivial) Instruction Set Assembly instruct. First byte Second byte Operation MOV Rn, direct 0000 Rn direct Rn = M(direct) MOV direct, Rn 0001 Rn direct M(direct) = Rn Rm MOV @Rn, Rm 0010 Rn M(Rn) = Rm MOV Rn, #immed. 0011 Rn immediate Rn = immediate ADD Rn, Rm 0100 Rn Rm Rn = Rn + Rm SUB Rn, Rm 0101 Rn Rm Rn = Rn - Rm JZ Rn, relative 0110 Rn relative PC = PC+ relative (only if Rn is 0) opcode operands ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

7. Addressing Modes Addressing mode Register-file contents Memory contents Operand field Immediate Data Register-direct Register address Data Register indirect Register address Memory address Data Direct Memory address Data Indirect Memory address Memory address Data ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

8. Sample Program C program Equivalent assembly program 0 MOV R0, #0; // total = 0 1 MOV R1, #10; // i = 10 2 MOV R2, #1; // constant 1 int total = 0; for (int i=10; i!=0; i--) total += i; // next instructions... 3 MOV R3, #0; // constant 0 Loop: JZ R1, Next; // Done if i=0 5 ADD R0, R1; // total += i 6 SUB R1, R2; // i-- 7 JZ R3, Loop; // Jump always Next: // next instructions... ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

9. Architecture of a Simple Microprocessor Datapath 1 Control unit 0 To all input control signals RFs 2x1 mux RFwa Controller (Next-state and control logic; state register) RF (16) RFw RFwe From all output control signals RFr1a RFr1e 16 RFr2a Irld PCld PC IR RFr1 RFr2 PCinc RFr2e ALUs PCclr ALU ALUz 2 1 0 Ms 3x1 mux Mre Mwe Memory D A • Storage devices for each declared variable • register file holds each of the variables • Functional units to carry out the FSMD operations • One ALU carries out every required operation • Connections added among the components’ ports corresponding to the operations required by the FSM • Unique identifiers created for every control signal Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction" ECE 448 – FPGA and ASIC Design with VHDL

10. A Simple Microprocessor Datapath 1 Control unit 0 To all input control signals RFs 2x1 mux RFwa Controller (Next-state and control logic; state register) RF (16) RFw RFwe From all output control signals RFr1a RFr1e 16 RFr2a Irld PCld PC IR RFr1 RFr2 PCinc RFr2e ALUs PCclr ALU ALUz 2 1 0 Ms 3x1 mux Mre Mwe Memory D A Reset PC=0; PCclr=1; IR=M[PC]; PC=PC+1 Fetch MS=10; Irld=1; Mre=1; PCinc=1; Decode from states below Mov1 RF[rn] = M[dir] RFwa=rn; RFwe=1; RFs=01; Ms=01; Mre=1; to Fetch op = 0000 RFr1a=rn; RFr1e=1; Ms=01; Mwe=1; Mov2 M[dir] = RF[rn] 0001 to Fetch RFr1a=rn; RFr1e=1; Ms=00; Mwe=1; Mov3 M[rn] = RF[rm] 0010 to Fetch Mov4 RF[rn]= imm RFwa=rn; RFwe=1; RFs=10; 0011 to Fetch RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=00 Add RF[rn] =RF[rn]+RF[rm] 0100 to Fetch RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs=01 Sub RF[rn] = RF[rn]-RF[rm] 0101 to Fetch PCld= ALUz; RFrla=rn; RFrle=1; Jz PC=(RF[rn]=0) ?rel :PC 0110 to Fetch FSM operations that replace the FSMD operations after a datapath is created FSMD You just built a simple microprocessor! ECE 448 – FPGA and ASIC Design with VHDL Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

11. PIC Microcontroller ECE 448 – FPGA and ASIC Design with VHDL

12. PIC Microcontroller implemented inside of an FPGA device STROBE = PORTC(0) FPGA PIC µController CLK RESET PORTC PORTB PORTA 7-Seg Decoder Display PORTA ECE 448 – FPGA and ASIC Design with VHDL

13. PIC Microcontroller Core MCLR CLK PROGRAM PICROM 256 x 12 CONTROL UNIT P C 8 Addr Address Bus Data DATA 12 REGFILE R8 Instruction Decoder Fsel 8 4 8 R31 FSR CONSTANTS OPCODES Din Dout W ALU Data Bus 8 4 8 8 EXTENDED ALU COMPUTATIONS PORTA PORTB PORTC 4 8 8 ECE 448 – FPGA and ASIC Design with VHDL

14. Flowchart of our PIC program RESET Set Port Directions Sum <= ‘0’ Counter <= ‘0’ Wait for a rising edge at Port C(0) Wait for a rising edge at Port C(0) Port B <= Sum(3 downto 0) N Port B <= Port A Sum <= Sum + Port A Counter <= Counter + 1 Wait for a rising edge at Port C(0) Counter = 8? Y Port B <= Sum(7 downto 4) ECE 448 – FPGA and ASIC Design with VHDL

15. Selected Registers of PIC ADDR  Working Register (Accumulator) W  Program Counter PC 05 PORTA Bidirectional Input/Output Ports 06 PORTB 07 PORTC 08 R8 09 R9 R10 0A Register File (General Purpose Registers) . . 1E R30 1F R31  TRISA Direction Registers for Ports A, B & C  TRISB  TRISC ECE 448 – FPGA and ASIC Design with VHDL

16. Selected PIC Instructions (1) MOVF f, d MOVF f, 1 f f <8,31> MOVF f, 0 k  <0,255> W MOVWF f MOVLW k W k MOVWF f MOVLW k f W ECE 448 – FPGA and ASIC Design with VHDL

17. Selected PIC Instructions (2) 0 CLRF f CLRF f f f <8,31> 0 CLRW CLRW W ECE 448 – FPGA and ASIC Design with VHDL

18. Selected PIC Instructions (3) INCF f, d f +1 INCF f,1 INCF f,0 W ECE 448 – FPGA and ASIC Design with VHDL

19. Selected PIC Instructions (4) ADDWF f, d W f ADDWF f, 1 ADDWF f, 0 + ECE 448 – FPGA and ASIC Design with VHDL

20. Selected PIC Instructions (5) ANDWF f, d W f ANDWF f, 1 ANDWF f, 0 and ECE 448 – FPGA and ASIC Design with VHDL

21. Selected PIC Instructions (6) SWAPF f, d SWAPF f, 1 fH fL SWAPF f, 0 W ECE 448 – FPGA and ASIC Design with VHDL

22. Selected PIC Instructions (7) GOTO label CALL label RETLW CALL label CALL label GOTO label label label label RETLW ECE 448 – FPGA and ASIC Design with VHDL

23. Selected PIC Instructions (8) BTFSC f, b f 7 b 0 f(b) = 0? BTFSC f, b No Next instruction Yes After-next Instruction ECE 448 – FPGA and ASIC Design with VHDL

24. Selected PIC Instructions (8) BTFSS f, b f 7 b 0 f(b) = 1? BTFSS f, b No Next instruction Yes After-next Instruction ECE 448 – FPGA and ASIC Design with VHDL

25. Selected PIC Instructions (9) TRISB TRISA TRISC 8 8 4 TRIS f W TRIS PORTA TRIS PORTC TRIS PORTB 1 – Input port bit direction 0 – Output port bit direction ECE 448 – FPGA and ASIC Design with VHDL

26. PIC Programming Environment Source File in the PIC Assembly Language *.ASM MPASM HEX File *.HEX *.LST Listing File MPSIM ECE 448 – FPGA and ASIC Design with VHDL

27. Questions? ECE 448 – FPGA and ASIC Design with VHDL