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FIR filters

FIR filters. ELG6163 Miodrag Bolic. Outline. FIR filters Structures Polyphase FIR filters Parallel polyphase FIR Decimated FIR Implementations of FIR filters. Sequential application specific processor. A processor tuned only for a particular application

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FIR filters

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  1. FIR filters ELG6163 Miodrag Bolic

  2. Outline • FIR filters • Structures • Polyphase FIR filters • Parallel polyphase FIR • Decimated FIR • Implementations of FIR filters

  3. Sequential application specific processor • A processor tuned only for a particular application • Can be used for low-power implementations • Word lengths can be adjusted to the current problem. • Example: FIR filter

  4. Direct form FIR filter Copied from [Wanhammer99]

  5. Transposed FIR Copied from [Wanhammer99]

  6. Assignment • Design an N-tap transposed linear-phase FIR filter as a sequential application specific processor. Use only one multiplier and show how processing time can be decreased twice. Hint: design a transposed FIR filter structure as in the previous slide but allow for generating the sums in reversed order PSN-1, PSN-2, …, PS1, y(n). Copied from [Wanhammer99]

  7. General purpose processor architecture • FIR example • We will study RISC architectures • Single-cycle processor • Implementation of add and load instructions • Pipelined implementation • Why do all instructions have the same number of cycles

  8. Example: Digital Filtering • The basic FIR Filter equation is Where h[k] is an array of constants y[n]=0; For (n=0; n<N;n++) { For (k = 0;k<N;k++) //inner loop y[n] = y[n] + h[k]*x[n-k];} Only Multiply and Accumulate (MAC) is needed! In C language Copied from Rony Ferzli: http://www.fulton.asu.edu/~karam/eee498/

  9. MAC using General Purpose Processor (GPP) R0 R2 44 X R1 Copied from Rony Ferzli: http://www.fulton.asu.edu/~karam/eee498/

  10. MAC using DSP • Harvard Architecture allows multiple memory reads R2 44 X Copied from Rony Ferzli: http://www.fulton.asu.edu/~karam/eee498/

  11. Copied from [DSPPrimer-Slides]

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