1 / 4

Design Constraint Analysis

Design Constraint Analysis. Team 6: AJ Hartnett David Eslinger Curt Schieler Ken Pesyna. FPGA Selection. Design Constraints Make design cheap Need multiple clocks (data in, compression) 12 bit parallel ADC and DAC, pins to communicate with uC, 10+ pins for FIFO SRAM

overton
Download Presentation

Design Constraint Analysis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Design Constraint Analysis Team 6: AJ Hartnett David Eslinger Curt Schieler Ken Pesyna

  2. FPGA Selection • Design Constraints • Make design cheap • Need multiple clocks (data in, compression) • 12 bit parallel ADC and DAC, pins to communicate with uC, 10+ pins for FIFO SRAM • Plan to do linear predictive coding, and rice coding on FPGA for speed purposes • Ability to quickly become familiar with product • Rationale • Cost • Number of PLLs • I/O pins • Number of registers/gates • TA experience • Existence of development kits at Purdue

  3. Parts for considerations • Altera: Cyclone III • >80 I/O pins • >20k registers • 4 PLLs • Karl has recent experience • Dev kits • $40-70 • Xilinx: Spartan 3a • >80 I/O pins • Low number logic blocks • Mike has non-recent experience • Dev kits • $25-50

  4. Winner • Altera Cyclone III • EP3C25E144C8N • 82 I/O pins • ~ 25k Logic blocks • 144-EQFP • $39.50

More Related