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Performance analysis

Performance analysis. outline. IP introduction Compare between different kinds of interface Compare between direction and non-direction Compare between different memory hierarchy Using FIFO full-cycles to improve the system SPARK survey. AES. Reed Solomon encoder/decoder.

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Performance analysis

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  1. Performance analysis

  2. outline • IP introduction • Compare between different kinds of interface • Compare between direction and non-direction • Compare between different memory hierarchy • Using FIFO full-cycles to improve the system • SPARK survey

  3. AES

  4. Reed Solomon encoder/decoder

  5. The compare between input master

  6. block diagram – input pipeline and output FIFO CPU Memory1 AVALON SWITCH FABRIC output master input pipeline master FIFO FIFO IP core

  7. block diagram – input pipeline and output FIFO CPU Memory1 AVALON SWITCH FABRIC 1 input master FIFO IP core Memory2 FIFO output master AVALON SWITCH FABRIC 2

  8. AES simple readmaster system

  9. AES pipeline readmaster system

  10. RS simple readmaster system

  11. RS pipeline readmaster system

  12. The compare between direct connection and non-direct connection

  13. Direction connection between IPs CPU Memory1 AVALON SWITCH FABRIC AEScipher RSencoder AESinvcipher RSdecoder

  14. AES-cipher and RS-encoder direct connection simple readmaster system

  15. AES-cipher and RS-encoder direct connection pipeline readmaster system

  16. AES-invcipher and RS-decoder direct connection simple readmaster system

  17. AES-invcipher and RS-decoder direct connection pipeline readmaster system

  18. AES and RS direct connection simple readmaster system

  19. AES and RS direct connection pipeline readmaster system

  20. IPs didn’t connect together CPU Memory1 AVALON SWITCH FABRIC AEScipher RSencoder RSdecoder AESinvcipher

  21. Non-direct connection design

  22. The compare between one memory or two memory

  23. out out input input FIFO FIFO FIFO FIFO IP core IP core Two IPs work concurrently CPU Memory1 AVALON SWITCH FABRIC

  24. Two IPs work concurrently CPU Memory1 AVALON SWITCH FABRIC out input out input FIFO FIFO FIFO FIFO IP core IP core AVALON SWITCH FABRIC Memory2

  25. The FIFO full-cycles analysis

  26. AES-cipher and RS-encoder AVALON SWITCH FABRIC 22285 Bottleneck FIFO AEScipher FIFO RSencoder FIFO Pipelineinputmaster Outputmaster 22277 0 FIFO_stop : 3 DSIZE : 4128 Average cycles : 28177 over 1024 times

  27. AES-cipher and RS-encoder- increase the data rate AVALON SWITCH FABRIC 0 FIFO AEScipher FIFO RSencoder FIFO Pipelineinputmaster Outputmaster RSencoder 0 0 FIFO_stop : 3 DSIZE : 4128 Average cycles : 19847 over 1024 times

  28. AES-cipher and RS-encoder direct connection 1 RS-encoder

  29. AES-cipher and RS-encoder direct connection 2 RS-encoder simple readmaster

  30. SPARK survey

  31. SPARK • I want to prove that the interface is suitable for HLS tool’s result. • SPARK has released their version v1.3. It contains more examples to illustrate how to use the tool. • There is an example min-sort illustrate the usage of array.

  32. SPARK – minsort brief introduction • Input function int a[8]; // array must be declared as an arrayvoid sort(int n){ ...} • Output module portCLOCKRESETN – an 32bit data, in portA – an 8-element array of 32-bit data, inout portDONE

  33. SPARK - signal • RESET is positive edge triggered. After reset the module, the IP start to work. • Once it finish the computation. It will raise the done signal. • The done signal is de-asserted by another reset.

  34. SPARK – minsort reslut CLOCKRESET DONE A – inout arrayN

  35. SPARK - problems • The problem is that the inout port array.

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