Smart Technologies for Effective Reconfiguration: The FASTER approach

1. Smart Technologies for Effective Reconfiguration:The FASTER approach May 29th – 31st 2013International Conference on IC Design and TechnologyPavia, Italy M. D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto http://www.fp7-faster.eu/

2. Reconfigurable Technology • Technology for adaptable hardware systems • Can add/removecomponentsatrun-time/productlifetime • Flexibilityat hardware speed (notquite ASIC) • Parallelismat hardware level (depending on application) • Ideally: alter function & interconnection of blocks • Implementation in: • FPGAs: fine grain, complex gate plus memory and DSP blocks • CoarseGrain (custom) chips: multiple ALUs, multiple (simple) programmable processing blocks, etc.

3. An issue as a new opportunity • Programming has become very difficult • Impossible to balance all constraints manually • More computational horse-power than ever before • Cores are free, reconfigurable logic available on chip, cores can be heterogeneous • Energy is new constraint • Software must become energy and space aware • Modern computing systems need to be flexible and adaptive • To optimize and meet their requirements taking advantage as much as possible of the underlying complex heterogeneous architectures

4. FASTER Motivation • Creating reconfigurable systems is not straightforward! • Reconfiguration cost is substantial (use wisely) • Tool support for these tasks is still quite basic • Resource management is up to the user • The designer has to: • Identifyportions to be reconfigured • Establish a schedule that (a) respectsdependencies (b) achieves performance and otherconstraints • Manage the system resources (also at run-time) • Verify a changing system!

5. FASTER Goals and Innovation • Include reconfigurabilityas an explicit design concept in computingsystems design, along with methods and toolsthatsupportrun-time reconfiguration in the entire design methodology • Provide a framework for analysis, synthesis and verification of a reconfigurablesystem • Provideefficient and transparentruntimesupport for partial and dynamicreconfiguration, including micro-reconfiguration • Demonstrate usability & performance on commercial applications and platforms (Maxeler, ST Microelectronics, Synelixis)

6. FASTER Platforms • Bridging the gap between HPC and embedded systems • Opportunities and challenges of reconfiguration in both the domains • High-Performance Computing Systems • Maxeler MPC MaxWorkstation • FPGA-based Embedded Systems • Xilinx University Program Board (XUPV5-LX110T) • AVNET Zedboard (SoC XC7Z020)

7. FASTER: Overall Methodology

8. Design Phase and Runtime Support • Define a reconfiguration-aware design methodology that exploits FPGAs: • Generate hardware and software components (including runtime support) on the top of existing vendor flows • Exploit dynamic reconfigurability for different target reconfigurable architectures. • Both HPC and embedded systems • Define and implement a new generation of self reconfigurable architectures based on Linux

9. System analysis and design • Annotated source code(C+OpenMP) .c .xml • Architecture • Additional application information Task Graph Generation DFG Extraction .xml Partitioning and Optimizations High Level Analysis Static Baseline Scheduling Run-time Support and Verification Mapping and Floorplanning • DFGs for HW blocks • Mapping Configurations .c • Source code for CPU .xml • HLS • System generation

10. Identifying Level of Reconfigurability Mapping T1 T2 T3 T4 T5 Architectural Template XML Platform Specification XML MAP MAP Library XML • Assigningeachtask of the application to the “best”processing element • Reconfiguration is implicitly considered • Based on a metaheuristic iterative algorithm Objectives: function of occupation area, execution time, power, number of reconfigurations etc... Convergence • Iterative, multi objectives: • Runtime • Power • Area • …

11. Micro-reconfiguration Optimization • In some applications we can identify hardware accelerators with slow‐changing “parameters” • Filter coefficients • Parameters trigger a small-scale reconfiguration • Design of cores based on Tunable FPGA blocks: • Identify parameters • Create bitfile with “holes” • Parameter values => reconfiguration bits for missing “holes” • Fine grain, faster reconfiguration time!

12. Verifying Reconfigurable Systems • Study design validation approaches: simulation, emulation and formal verification • Extend symbolic simulation to dynamic aspects of reconfigurable design • In some cases static approaches may not be able to verify the entire RC system • We use run‐time verification. Address and minimize impact on: • Speed, area and power • Light‐weight architectural support

13. Run-time System • Evaluate reconfiguration overhead • Propose advanced mechanisms to support • Scheduling • Dynamic reconfiguration (including micro-reconfiguration) • Run-time verification • Provide run-time support for dynamic reconfiguration based on static analysis • Extension of OS capabilities • Efficient on-line scheduling and placement of task modules

14. OS-based Management • Provide software support for dynamic partial reconfiguration on a Linux-based operating systems • Reconfiguration process managed from the OS in a transparent way • Hardware-independent interface for software developers based on the GNU/Linux • Addition and removal of reconfigurable components • Easier programming interface for specific drivers • OS customization for specific architectures

15. Expected Results and Conclusions • FASTER is a focusedprojectthatbuilds on combinedpartners expertise aswellas on pastresearch work and projects • We focus on (and hope to demonstrate): • productivityimprovement in implementation and verification of dynamicallychangingsystems • totalownershipcostreduction (NIDS and RTM systems) • performance improvement under powerconstraints for Global Illumination and Image Analysis application

16. Challenges & Opportunities • Tool support for analysis and system definition • Specification of changing system(s) • Reconfigurable granularity: influenced by tools and applications • Architectural support for reconfiguration (vendor?) • Metrics: include design effort/time, total ownership cost