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Asynchronous Circuits

Asynchronous Circuits. Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona Collège de France May 14 th , 2013. Goals. Convince ourselves that: designing an asynchronous circuit is easy synchronous and asynchronous circuits are similar

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Asynchronous Circuits

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  1. Asynchronous Circuits Jordi Cortadella Universitat Politècnica de Catalunya, Barcelona Collège de FranceMay 14th, 2013

  2. Goals • Convince ourselves that: • designing an asynchronous circuit is easy • synchronous and asynchronous circuits are similar • asynchronous circuits bring new advantages • Not to discourage designers with exotic and sophisticated asynchronous schemes Asynchronous circuits

  3. Clocking • How to distribute the clock? • How to determine the clockfrequency? • How to implement robustcommunications? • How to reduce and manageenergy? NvidiaKeplerTM GK110 28nm, 7.1B transistors, 550mm2, 2688 CUDA cores, Base clock: 836MHz, Memory clock: 6GHz Asynchronous circuits

  4. … time is elastic … Asynchronous circuits

  5. Synchronous circuits

  6. Synchronous circuit Flip Flops CombinationalLogic Flip Flops PLL Asynchronous circuits

  7. Synchronous circuit CL • Two competing paths: • Launching path • Capturing path Launching path < Capturing path + Period CLKtree + CL < CLKtree+ Period 1 2 PLL 2 1 1 2 (no clock skew) CL < Period Asynchronous circuits

  8. Source-synchronous Launching path Capturing path CLKgen matched delay matched delay matched delay • No global clock required • More tolerance to PVT variations • Period > longest combinational path • Good for acyclic pipelines Asynchronous circuits

  9. Source-synchronous with forks and joins CLKgen ? How to synchronize incoming events? Asynchronous circuits

  10. C element (Muller 1959) A C C B A B C Asynchronous circuits

  11. C element (Muller 1959) A MAJ B C (many implementations exist) A B C Asynchronous circuits

  12. Multi-input C element a1 a2 a3 C C C C C C a4 c a5 a6 a7 Asynchronous circuits

  13. Completion detection

  14. Completion detection CLK gen fixed delay The fixed delay must be longer than theworst-case logic delay (plus variability) Q: could we detect when a computation has completed ASAP ? Asynchronous circuits

  15. Delay-insensitive codes: Dual Rail • Dual rail: every bit encoded with two signals A.t A.f A 1 SP 0 SP 1 SP 1 SP Asynchronous circuits

  16. Dual-Rail AND gate A.t C.t A.f B.t C.f B.f A C B Asynchronous circuits

  17. Dual-Rail Inverter A.t Z.t Z.f A.f Asynchronous circuits

  18. Dual-Rail AND/OR gate A.t C.t A.f A C B B.t C.f B.f A A.f C C.f A.t B  B.f C.t A B.t C B Asynchronous circuits

  19. Dual rail: completiondetection Dual-rail logic 00 01 00 10 00 10 00 01 00 10 00 01 00 01 00 01 00 10 10 00 • • • 00 01 • • • 00 01 10 00 Asynchronous circuits

  20. Dual rail: completiondetection done C Completion detection tree Dual-rail logic • • • • • • Asynchronous circuits

  21. Dual rail: completion detection AND AND INV OR CLK gen Asynchronous circuits

  22. Dual rail: completion detection AND AND INV OR C C Asynchronous circuits

  23. Single rail data vs. dual rail Some back-of-the-envelope estimations: • Dual rail: • Good for speed • Large area • High power comsumption Asynchronous circuits

  24. Handshaking

  25. Handshaking CLK gen unknown delay • Assume that the source module can provide data at any rate: • When should the CLK generator send an event if theinternal delays of the circuit are unknown? • Solution:handshaking Asynchronous circuits

  26. Handshaking Data I have data Request Acknowledge I want data Asynchronous circuits

  27. Asynchronous elastic pipeline ReqIn ReqOut C C C C AckOut AckIn • David Muller’s pipeline (late 50’s) • Sutherland’s Micropipelines (Turing award, 1989) Asynchronous circuits

  28. Multiple inputs and outputs Asynchronous circuits

  29. Multiple inputs and outputs delay Asynchronous circuits

  30. Channel-based communication • A channel contains data and handshake wires Data Req Ack Data Req Ack Asynchronous circuits

  31. Two-phase protocol • Every edge is active • It may require double-edge triggered flip-flops or pulse generators Data transfer Data transfer Req Ack Data 3 Data 1 Data 2 Data Asynchronous circuits

  32. Four-phase protocol • Valid data on the active edge of Req • Req/Ack must return to zero before the next transfer • Different variations of the 4-phase protocol exist Data transfer Data transfer Req Ack Data 3 Data 1 Data 2 Data Asynchronous circuits

  33. How to memorize? L CombinationalLogic L ? ? C C delay 2-phase or 4-phase ? Asynchronous circuits

  34. How to memorize? L CombinationalLogic L Pulsegenerator C C delay 2-phase Asynchronous circuits

  35. How to memorize? L CombinationalLogic L C C delay 4-phase Asynchronous circuits

  36. Performance analysis

  37. Ring oscillators C 7 6 5 1 C C C 3 4 C 2 • Every ring requires an odd number of inverters • The cycle period is determined by the slowest ring • The cycle period is adapted to the operating conditions(temperature, voltage) Asynchronous circuits

  38. Why asynchronous?

  39. Modularity • Time-independent functional composability • Performance may be affected (but not functionality) B’ B A Data Req Ack Asynchronous circuits

  40. Tracking variability matched delay Asynchronous circuits

  41. Tracking variability delay • Good correlation for: • Process variability (systematic) • Global voltage fluctuations • Temperature • Aging (partially) multi-corner matched delay critical paths best typ worst Asynchronous circuits

  42. Margins Rigid Clocks: Gate and wire delays (typ) P V T PLLJitter Aging Skew Cycle period Elastic Clocks: Margin reduction Skew Gate and wire delays (typ) P V T Aging Speed-up / Power savings Cycle period Asynchronous circuits

  43. Clock elasticity Rigid clock wasted time computation time Cycle period Elastic clock computation time Cycle period Asynchronous circuits

  44. Voltage scaling and power savings 3 ARM926 coreson the same die -14% -24% Asynchronous circuits

  45. Design Automation

  46. Design automation paradigms • Synthesis of asynchronous controllers • Logic synthesis from Petri nets orasynchronous FSMs • Syntax-directed translation • Correct-by-construction composition of handshake components • De-synchronization • Automatic transformation from synchronous to asynchronous Asynchronous circuits

  47. Synthesis of asynchronous controllers DSr DSr+ DTACK- LDS LDTACK LDS+ LDTACK+ D+ DTACK+ DSr- D- D LDTACK- LDS- DTACK Asynchronous circuits

  48. Synthesis of asynchronous controllers DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D DTACK Example: Petrify LDS DSr LDTACK Asynchronous circuits

  49. Syntax-directed translation P = (A || B) ; C (A || B) ; C Asynchronous circuits

  50. Syntax-directed translation P = (A || B) ; C seq A || B C par B A Asynchronous circuits

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