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Digital Integrated Circuit Design

Digital Integrated Circuit Design. Andrea Bonfanti DEIB Via Golgi 40 Milano. The Inverter. V. DD. V. V. in. out. C. L. The CMOS Inverter: A First Glance. V. DD. CMOS Inverter. N Well. PMOS. 2 l. Contacts. Out. In. Metal 1. Polysilicon. NMOS. GND. Two Inverters.

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Digital Integrated Circuit Design

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  1. Digital Integrated Circuit Design Andrea Bonfanti DEIB Via Golgi 40 Milano The Inverter

  2. V DD V V in out C L The CMOS Inverter: A First Glance

  3. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  4. Two Inverters Shared power and ground Abut cells Connect in Metal

  5. V V DD DD R p V out V out R n V V V 0 5 5 in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp)

  6. t = f(R .C ) pHL eq L = 0.69 R C eq L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n V 0 V V 5 5 in DD in (a) Low-to-high (b) High-to-low

  7. Voltage TransferCharacteristic

  8. I Dn V = V +V in DD GSp I = - I Dn Dp V = V +V out DD DSp V out I I I Dp Dn Dn V =0 V =0 in in V =1.5 V =1.5 in in V V V DSp DSp out V =-1 GSp V =-2.5 GSp V = V +V V = V +V in DD GSp out DD DSp I = - I Dn Dp PMOS Load Lines

  9. CMOS Inverter Load Characteristics

  10. CMOS Inverter VTC

  11. 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Switching Threshold as a function of Transistor Ratio 3.5

  12. V out V OH V M V in V OL V V IL IH Determining VIH and VIL A simplified approach

  13. Inverter Gain

  14. Gain=-1 Gain as a function of VDD

  15. Simulated VTC

  16. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  17. Propagation Delay

  18. V DD t = f(R C ) pHL eq L = 0.69 R C eq L V out V ln(2) out C L 1 V R DD eq 0.5 0.36 V = V in DD t R C eq L CMOS Inverter Propagation Delay

  19. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  20. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpHL tpLH

  21. Design for Performance • Keep capacitances small • Increase transistor sizes • watch out for self-loading! • Increase VDD (????)

  22. Delay as a function of VDD

  23. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  24. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn

  25. Impact of Rise Time on Delay Wn=0.375um Wp=1.125um

  26. Inverter Sizing

  27. Inverter Chain In Out CL If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? May need some additional constraints

  28. Minimum inverter delay • Minimum length devices, L=0.25m • Assume WP = 3WN =3W =0.75m (!!) • same pull-up and pull-down currents • approx. equal resistances, i.e. RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 3W W tpHL = (ln 2) RNCint(1) Delay (D): tpLH = (ln 2) RPCint(1)

  29. Inverter without load Delay Req 3W Cint W Req W(0) W tp = kReqCint k is a constant, equal to 0.69 Intrinsic delay does not change with W: Req decreases with W while Cint increases with W

  30. Inverter with load Delay 3W tp0 Cint CL W CL tp=0.69Req(Cint + CL)=0.69ReqCint+0.69ReqCL=0.69ReqCint(1+ CL/Cint) = Delay (Internal) + Delay (Load)

  31. Delay Formula Cint = g Cg withg 1 f = CL/Cg- effective fanout R = Req(1) (W(1)/W); Cint = Cint(1)(W/W(1)) tp0 = 0.69Req(1)Cint(1)

  32. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

  33. Optimal tapering for a given N Delay equation has N - 1 unknowns, Cg,2 – Cg,N Minimize the delay, find N - 1 partial derivatives Result: Cg,j+1/Cg,j = Cg,j/Cg,j-1 Size of each stage is the geometric mean of two neighbors • each stage has the same effective fanout (Cout/Cin) • each stage has the same delay

  34. Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay

  35. Example in out s s2 1 CL= 8 Cg(0) Cg(1) CL/Cg(1) has to be equally distributed across N = 3 stages: Since the first inverter is minimum:

  36. Example: not-minimum input stage in out 2 s s2 CL= 8 Cg= 16 Cg(1) Cg but since the first inverter is not minimum:

  37. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

  38. Optimum Effective Fanout f Optimum f for given process defined by g fopt fopt = 3.6 forg=1 g

  39. Impact of self-loading on tp no self-loading, g=0 with self-loading g=1 F=1000 F=1000 F=100 F=100 F=10 F=10

  40. Normalized delay function of F

  41. Buffer Design N f tp/tp0 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 64 16 1 64 22.6 8 2.8

  42. Power Dissipation

  43. Where Does Power Go in CMOS?

  44. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes Need to reduce C , V , and f to reduce power. L dd

  45. Modification for Circuits with Reduced Swing

  46. Adiabatic Charging 2 2 2

  47. Adiabatic Charging

  48. Node Transition Activity and Power

  49. Transistor Sizing for Minimum Energy • Goal: Minimize Energy of whole circuit • Design parameters: f and VDD • tp tpref of circuit with f=1 and VDD =Vref

  50. Transistor Sizing (2) • Performance Constraint (g=1) • Energy for single Transition

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