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Software Tools for CM Standardization

Software Tools for CM Standardization. Laurent Lemaitre. Contents. Verilog-AMS: Brief Introduction ADMS: open-source tool that facilitates compact model introduction and maintenance of compact models

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Software Tools for CM Standardization

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  1. Software Tools for CM Standardization Laurent Lemaitre

  2. Contents • Verilog-AMS: Brief Introduction • ADMS: open-source tool that facilitates compact model introduction and maintenance of compact models • ZSPICE: simple spice simulator that facilitates bench- marking and distribution of new compact models • Conclusion

  3. What is Verilog-AMS? • Verilog-AMS is a hardware description language used as a behavioral language for analog circuit simulators • Verilog-AMS gives analog designers a means to encapsulate behavioral description of analog systems into modules • Verilog-AMS can be re-used for compact device modeling: L. Lemaitre, ADMS – Automatic Device Model Synthesizer, cicc2002 M. Mierzwinski, Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A, nanotech2003 K. Kundert, Automatic Model Compilation, An Idea Whose Time has Come www.designers-guide.com • More info at http://www.accellera.org/

  4. Verilog-AMS - Code Example `include "std.va" `include "const.va" module mosfet (d,g,s,b); inout           d,g,s,b ;   // external nodes electrical      d,g,s,b ;   // external nodes real x, VG, VS, VD, VGprime, VP; real beta, n, iff, ir, Ispec, Id; parameter real VTO    =  0.5    from[0.0:inf]; parameter real GAMMA  =  0.7    from[0.0:inf]; parameter real PHI    =  0.5    from[0.2:inf]; analog begin VGprime = VG - VTO + PHI + GAMMA * sqrt(PHI); beta = KP * (W/L) * (1.0/(1.0 + THETA * VP)); x=(VP-VS)/$vt; iff = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0))); x=(VP-VD)/$vt; ir  = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0))); Ispec = 2 * n * beta * $vt * $vt; Id = Ispec * (iff - ir); I(d,s) <+ Id; end // analog endmodule

  5. Benefits Using Verilog-ASM • For the model developer • Develop once and run everywhere • Focus on model equation, not on implementation • For the software vendors • Simplified implementation of the standard models • Proprietary Verilog-A models are also supported • For the silicon fab • Standardized model parameter set • For the end-users (designers) • Standardized libraries and design kits

  6. ADMS - Basics http://sourceforge.net/projects/mot-adms/ ADMS: Project Summary ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. 120 downloads in two weeks (start September 03)

  7. ADMS - Overview Verilog-AMS Source Code ADMS Parser ADMS Data Base XML Internal data ADMS-XML Simulator-specific Interfaces Other ADMS-XML Interfaces Other Code Generator applications Testing prior implementation C code Mica, Spectre, ADS, Zspice Documentation Circuit Test Benches

  8. ADMS - getting xml interfaces • xml interfaces available for • SPECTRE-CADENCE and ADS-AGILENT • CADENCE • contact CADENCE support & sign NDA • request for DPI kit (spectre interface) + xml files • AGILENT • contact AGILENT support • the xml files target the public interface of ADS (no need to download it)

  9. Zspice - Introduction http://sourceforge.net/projects/mot-zspice/ Zspice: Project Summary Zspice is a simple reconfigurable spice simulator. Its device library is automatically generated using ADMS, a software tool available on SourceForge.net. More can be found at: http://legwww.epfl.ch/ekv/mos-ak/crolles/06_ll_mos-ak03.ppt

  10. Zspice - Overview zspice netlist zspice zspiceZkt_dc.xml results in zspice format admsXml zspice c file zspiceModuleC.xml zsp library cc zspice h file svg.pl zspiceModuleH.xml results in SVG format verilog-ams module SVGviewer displays the results inside a web browser zspiceBasic.h zspiceMath.h zspiceInterface.h

  11. Zspice - Results Available Compact Models EKV team plan to release EKV 3.0 using ZSPICE in October

  12. Zspice - Spice-like Output re-use of existing freeware SVGviewer inside internet explorer

  13. Work in Progress Verilog-AMS subcommittee: • started April 2003 • mission: extend verilog-AMS to cover compact device modeling • adms and zspice proposed as test vehicle for the new language • adms and zspice is open-source software (sourceforge.net) • adms and zspice developments under the umbrella of this subcommittee Interested Parties: • Motorola - Mica • Cadence - Spectre • Agilent - ADS • Nassda - hsim • Xpedion - GoldenGate • Mentor - Eldo • Helsinki University of Technology - Aplac • University of Washington – spice3 interface

  14. Conclusion • Two open-source tools have been presented • Both tools are available on SourceForge.net • The development of both projects is very active • Visit frequently the SourceForge.net web sites • FREE tool downloads • Your feedback is welcome

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