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A multi-chip board for X-ray imaging in build-up technology

A multi-chip board for X-ray imaging in build-up technology. Alessandro Fornaini, Ton Boerkamp, Jan Visschers - NIKHEF Rui de Oliveira - CERN. Alessandro Fornaini, NIKHEF, Amsterdam 4 th International Workshop on Radiation Imaging Detectors. Hybrid Pixel detectors.

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A multi-chip board for X-ray imaging in build-up technology

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  1. A multi-chip board for X-ray imaging in build-up technology Alessandro Fornaini, Ton Boerkamp, Jan Visschers - NIKHEF Rui de Oliveira - CERN Alessandro Fornaini, NIKHEF, Amsterdam 4th International Workshop on Radiation Imaging Detectors

  2. Hybrid Pixel detectors Semiconductor sensor High purity, single crystal (Si, GaAs, ..) Pixel diode Xray 55 mm 300 - 600 mm Bumps Single pixel Read Out cell CMOS electronics Single photon counting 1

  3. Hybrid Pixel detectors (2) Problem: size limitations! Sensor size: not a problem (~15 cm diam. high res. Si) CMOS chip size: max. 25 x 25 mm2 due to reticle size of wafer stepper (Medipix2: 0.25mm technology, area 14 x 16 mm2) • Non-standard production techniques (“stitching”) to • circumvent this but: • Expensive • Yield inversely proportional to chip area! (due to • density of point defects and contaminations) 2

  4. 3.3V Muros2 Our solution: tiled array of chips Medipix2 setup: Si sensor, 28 x 56 mm2 Bump bonded Chipboard with 2 X 4 tiled ASIC chips Medipix2 512 x 1024 Pixels Bias PC with Medisoft4 and NI DIO card Muros2 interface 3

  5. Other tiled arrays 4

  6. Medipix2 setup 8 Medipix2 ASIC chips, 14 X 16 mm2 1 High Res. Si sensor, 28 X 56 mm2 Chipboard in Chip-on-Board technology Interface card to PCI DIO card (Muros2) Sensor bias voltage supply (commercial) PC with HS DIO board (commercial)

  7. Medipix2 Interconnectivity LVDS (Low Voltage Differential Signal) Reduce: noise generation, noise sensitivity, interconnectivity Better performance for large arrays Serial Daisy Chain Token passing protocol (LVDS) 160 Mhz CLK 1 Mbit data per chip 160 Mhz  160/Ntot frames/sec Medipix2 chip #N Medipix2 chip #N+1 DATA CLK ENABLE Common single-ended CMOS bus: shutter, mode control, reset, polarity and analog signals (test input, DAC output) 5

  8. 5 4 Layers 3, 4, 5 metal: Common CMOS bus 6 3 7 2 1 8 Connector Routing Top layer metal 1, 2: Vdd, Gnd and LVDS token ring 160 Mhz! Chip-on-Board (COB) technology Pitch of wirebonds = 120 mm, NO FANOUT Interconnection: High Density Interconnect (HDI) technology 6

  9. Interconnections High Density Interconnect (HDI) Build-up technology From: IPC/JPCA-2315 Design Guide for High Density Interconnects (HDI) Staggered Micro-Via’s (photolitographic etching) 7

  10. Multilayer board Beryllium Foil Vbias < 6 mm Box Pixel Sensor clock VDD-LVDS Medipix 2 token VDD Controls VDDA data GND Gnd Gnd busX busY busX VDD VDDA VDDL GND Peltier Cooler Capacitor FET switch 9 layers (4 metal, 5 build-up) 8

  11. Test Pulse FET switch DAC 1 to input analog test Medipix2 chip DAC 2 FPGA Medipix2 chipboard Muros2 9

  12. Multilayer board (2) 1.6 mm total thickness, area 53 x 110 mm2 10

  13. through via micro via's & Bond Pads VDDA spare clock token data Capacitor Via’s and Tracks dimensions 1840 micro-via’s 366 through via’s 80 SMD capacitors 8 CMOS FET’s 11

  14. Chipboard layout Chip bond pads Power bars Decoupling capacitors LVDS pairs FET switch, capacitors Test points 1 cm 12

  15. Chipboard layout Vbias connector 1 cm SCSI-5 connector 2 x 4 Medipix2 chip array 13

  16. … and the actual chipboard Power bars Vbias connector SCSI-5 connector 2 x 4 MPix2 chip array LVDS pairs 1 cm 14

  17. 1 cm Power bars LVDS pairs 15

  18. 1 cm 16

  19. Work in progress! Currently: - Evaluating different glues - Gluing and wire bonding - Testing LVDS line with 8 Medipix2 chips (no sensor) mounted on the chipboard Planning (~ 1 month): Testing connections with MPix2 chips Critical: communication speed tests (160 Mhz?) Status 16 prototypes boards produced at CERN Connectivity tests performed on 3 boards: NO DESIGN ERRORS! But: production defects (1 short, 2 connections - easily solvable) 17

  20. 16 Medipix2 2 x 4 chipboards have been produced. Testing is still going on but up to now results are very promising Conclusion A 2 x 2 sensor will be mounted and tested. We expect to have a 2 x 4 multichipboard running in ~ 6 months 18

  21. Tiled array: chips boundary Chip separation: 220 mm (4 pixels) Sensor: pixels at boundary 55 x 55 mm2 55 x 165 mm2 165 mm 220 mm 55 mm NO DEAD AREAbut: non uniformity (resolution, overflow)

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