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Stability and Scalability in Global Routing

Stability and Scalability in Global Routing. S. K. Han 1 , K. Jeong 1 , A. B. Kahng 1,2 and J. Lu 2 1 ECE Department, UC San Diego 2 CSE Department, UC San Diego System-Level Interconnect Prediction Workshop June 5, 2011. Outline. Motivation Routing Estimation Experiments Conclusions.

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Stability and Scalability in Global Routing

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  1. Stability and Scalability in Global Routing S. K. Han1, K. Jeong1, A. B. Kahng1,2 and J. Lu2 1ECE Department, UC San Diego 2CSE Department, UC San Diego System-Level Interconnect Prediction Workshop June 5, 2011 UCSD VLSI CAD Laboratory – SLIP 2011

  2. Outline • Motivation • Routing Estimation • Experiments • Conclusions UCSD VLSI CAD Laboratory – SLIP 2011

  3. Motivation: Evaluation of Routability • Routability: whether a placed design is routable? • Must avoid unroutable placement results • Loop back to placement after routing fails == too expensive! • Routability determination during placement is critical but difficult • Built-in congestion estimators in modern placers Placement Result Routing Result UCSD VLSI CAD Laboratory – SLIP 2011

  4. Congestion Estimation During Placement • Static, non-constructive • Fixed L-Z shape models • Equal-probability models • #bends-based probabilistic models • Testcase-independent models  too wide a gap between estimates and actual routing outcomes • Constructive • Integrated global router (under the hood of placement tool) • Helps P&R convergence  global router must be high-quality and fast to serve in this role UCSD VLSI CAD Laboratory – SLIP 2011

  5. This Work • How good can a routing estimator be? • One way to answer this question: How noisy or inherently unpredictable is the routing (or, router) that we’re trying to estimate? • We experimentally access “inherent unpredictability”: • Routing grid offset noise • Routing resource noise • Routing instance scaling • We discover stability, scalability limits of global routers UCSD VLSI CAD Laboratory – SLIP 2011

  6. Testbed (based on ISPD Global Routing Contest) • Routing quality metrics • TOF (total overflow) • MOF (maximum gedge-overflow) • WCI(A) (Worst congestion index) • U(A) (Average net-score) • ISPD-2008 Global Routing Benchmark Suite • Four academic global routers • FastRoute-4.1 • NTHU-2.0 • FGR-1.2 • NTUgr-1.1 UCSD VLSI CAD Laboratory – SLIP 2011

  7. Experiment 1: Offset Noise • Estimation on stability to grid-offset noise • Shift the origin of the gcell array horizontally and vertically • Constraint on offset: all pins should be covered Rightmost and Topmost pin location from benchmark Gx X Gy Leftmost and Bottommost pin location from benchmark Gcell Y-Dimension: 40 (0,0) Gcell X-Dimenson: 40 UCSD VLSI CAD Laboratory – SLIP 2011

  8. Offset Noise Experimental Results UCSD VLSI CAD Laboratory – SLIP 2011

  9. Experiment 2: Resource Noise • Add d units to both blockage and capacity to all the gedges • Effective capacity of every gedge is unchanged • Global routing problem should not be different, from router viewpoint 39 39 38 38 39 39 38 38 38 38 38 38 38 38 38 38 39 39 39 39 39 39 Blockage: d = 1 39 39 UCSD VLSI CAD Laboratory – SLIP 2011

  10. Resource Noise Experimental Results UCSD VLSI CAD Laboratory – SLIP 2011

  11. Experiment 3: Instance Scaling • Simple scaling of X1 benchmark  X2 benchmark • Duplicate all pins and nets of the original benchmark • Double the capacity and blockages of gedges • Twice the X1 solution cost is an upper bound on the optimum X2 solution cost 408 408 204 204 408 408 408 408 408 408 204 204 Original X1 Benchmark 408 408 X2-Scaled Benchmark UCSD VLSI CAD Laboratory – SLIP 2011

  12. Instance Scaling Experimental Results UCSD VLSI CAD Laboratory – SLIP 2011

  13. Conclusions • Study stability and scalability of four global routers • There are room for router improvement • Possible reasons leading to instability • Testcase-specific parameter tuning • Knobs tuning on one benchmark may lose its advantage on others • Over-reduction of congestion (reflects ISPD contest metric) • Unnecessary detours and over-sensitivity • Routability estimation allows moderate congestion (WL within 10% extension) • Unstable metrics • TOF, MOF, WCI(100), U(20) all vary significantly over different gcell definitions • New metrics with better stability are needed to facilitate future work UCSD VLSI CAD Laboratory – SLIP 2011

  14. THANK YOU UCSD VLSI CAD Laboratory – SLIP 2011

  15. References • [1] H.-M. Chen, H. Zhou, F. Y. Young, D. F. Wong, H. H. Yang and N. Sherwani, “Integrated Floorplanning and Interconnect Planning”, Proc. IEEE/ACM ICCAD, 1999, pp. 354-357. • [2] Kusnadi and J. D. Carothers, “A Method of Measuring Nets Routability for MCM’s General Area Routing Problems”, Proc. ISPD, 1999, pp. 186-194. • [3] J. Lou, S. Thakur, S. Krishnamoorthy and H. S. Sheng, “Estimating Routing Congestion Using Probabilistic Analysis”, IEEE TCAD, 21(1) (2002), pp. 32-41. • [4] A. B. Kahng and X. Xu, “Accurate Pseudo-Constructive Wirelength and Congestion Estimation”, Proc. SLIP, 2003, pp. 61-68. • [5] J. Westra, C. Bartels and P. Groeneveld, “Probabilistic Congestion Prediction”, Proc. ISPD, 2004, pp. 204-209. • [6] C.-W. Sham, F. Y. Young and J. Lu, "Congestion Prediction in Early Stages of Physical Design", ACM TODAES, 13(1) (2009), pp. 1-18. • [7] M. Pan and C. Chu, “IPR: An Integrated Placement and Routing Algorithm”, Proc. ACM/IEEE DAC, 2007, pp. 59-62. • [8] M. Wang and M. Sarrafzadeh, “Modeling and Minimization of Routing Congestion”, Proc. ACM/IEEE DAC, 2000, pp. 185-190. • [9] G.-J. Nam, C. Sze and M. Yildiz, “The ISPD Global Routing Benchmark Suite”, Proc. ISPD, 2008, pp. 156-169. • [10] Y. Xu, Y. Zhang and C. Chu, “FastRoute 4.0: Global Router with Efficient Via Minimization”, Proc. IEEE/ACM ASPDAC, 2009, pp. 576-581. • [11] Y.-J. Chang, Y.-T. Lee and T.-C. Wang, “NTHU-Route 2.0: A Fast and Stable Global Router”, Proc. IEEE/ACM ICCAD, 2008, pp. 338-343. UCSD VLSI CAD Laboratory – SLIP 2011

  16. References • [12] J. A. Roy and I. L. Markov, “High-Performance Routing at Nanometer Scale”, Proc. IEEE/ACM ICCAD, 2007, pp. 496-502. • [13] C.-H. Hsu, H.-Y. Chen and Y.-W. Chang, “High-Performance Global Routing with Fast Overflow Reduction”, Proc. IEEE/ACM ASPDAC, 2009, pp. 582-587. UCSD VLSI CAD Laboratory – SLIP 2011

  17. Problem Formulation • Routing grid modeling • Decomposition of design area • Mapping of rectangles into gcells (global cells) • Other parameters • gedges (global edges ), gedge capacity , gedge overflow UCSD VLSI CAD Laboratory – SLIP 2011

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