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Status of measurements of FE-I4 SEU and PRD

Status of measurements of FE-I4 SEU and PRD. A.Rozanov 16.05.2011. Measurements. Two FE-I4 chips installed in the PS beam Irrad3 Chip ID28 (PC marslhc ) Chip ID27 (PC marnach ) Also chip SEU3D installed Order in the beam ID27,ID28,SEU3D Al foils on ID27 and SEU3

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Status of measurements of FE-I4 SEU and PRD

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  1. Status of measurements of FE-I4 SEU and PRD A.Rozanov 16.05.2011

  2. Measurements • Two FE-I4 chips installed in the PS beam Irrad3 • Chip ID28 (PC marslhc) • Chip ID27 (PC marnach) • Also chip SEU3D installed • Order in the beam ID27,ID28,SEU3D • Al foils on ID27 and SEU3 • Orientation: EOC on the top, beam traverse first PCB, second the chips • Horizontal beam position in the center (columns 39/40) • Vertical beam position 5mm down from the center (far from EOC) • Beam size 12x12 mm • Start beam Thursday 12 may 2011

  3. Beam properties • Supercycle with 36x1.2=43.2 sec period • But sometimes is changing • Typical 2 bunches of 40 x 10 10 protons • But sometimes 3-4 bunches • Typical bunch positions: 4, 6,14,26 • Bunch length 400 msec • One iteration 2 (or 3) supercycles, 2-4 bunches per supercycle

  4. Timing Problems • Slow (3-4 sec) readout of double columns probably due to writing into RootDb and memory leaks in STControl. With unstable beam time structures superpositions during Latch readout and latch writing are possible. • Solutions: negotiate better time structure, change soft to sequential file writing, search for memory leaks, optimising readout sequence

  5. Harware problems • Frequent hang-ups of STControl • On chip ID 28 Vdda1=Vdda2=1.3 V at start. During running go down to 1.0V, while setting is at 1.5V. Idda=142 mA Broken voltage regulator???? (Normal Vddd=1.5 v, Iddd=340mA) • Chip ID27 stop to work Sunday morning. No USB connection.

  6. Very preliminary SEU results chip#28 • Run 16, two DCs (first in readout to avoid beam during readout, but beam during writing not excluded) • Type A(old) DC28 bit TDAC[1] • Type B(new) DC31 bit TDAC[1] • Statistics for 42 iterations (more 90 supercycles) • Normal SEU (<100 errors/bunch) • Coherent SEU(>100 errors/bunch typical 336, 293 ,175, 168)

  7. Very preliminary SEU results chip#28 • Normal SEU per iteration 130-260 10 10 protons • Type A 402/43= 9.3 seu/iteration/672bits • Type B 24/42= 0.6 seu/iteration/672bits • Coherent SEU • Type A 5/43= 0.12 events/iteration • Type B 15/42 = 0.36 events/iteration • More runs should be analysed • One should prove that SEU are not due to beam superposition during SR writing/loading

  8. Very preliminary radiation monitoring results • Chip#27, run 11, normal beam position PRD counts ~ 140 counts /iteration • Chip#27, run 11, beam position on PRD counts ~ 400 counts /iteration ,for first 12 iterations (but zero for 13 later iterations, should analyse if it was forced reset or not) • Chip#27 run 14, normal beam position PRD counts ~46/iteration

  9. Conclusions • Need more analysis of existing data • Too earlier for final conclusions • Should improve readout speed (or beam veto) to avoid beam superposition • Negociate better beam structure • More runs at PRD position ???

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