Hardware Design

1. Hardware Design This material exempt per Department of Commerce license exception TSU

2. Objectives After completing this module, you will be able to: • List the functionality that defines an arbiter, a master, and a slave • List the various buses available in the MicroBlaze processor • Discuss the six configurations of the MicroBlaze processor

3. Outline • Buses 101: Arbiter, Master, Slave • On-Chip Peripheral Bus (OPB) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations • PowerPC Processor Programmer’s Model • Reset Logicin the PowerPC Processor • JTAG Configurations in the Virtex-II Pro Device

4. Buses 101 • A bus is a multiwire path on which related information is delivered • Address, data, and control buses • Processor and peripherals communicate through buses • Peripherals may be classified as: • Arbiter, master, slave, or master/slave (bridge) Arbiter Arbiter Master Master/ Slave Master Slave Slave Slave

5. Buses 101 • Bus masters have the ability to initiate a bus transaction • Bus slaves can only respond to a request • Bus arbitration is a three-step process: • A device requesting to become a bus master asserts a bus request signal • The arbiter continuously monitors the request and outputs an individual grant signal to each master according to the master’s priority scheme and the state of the other master requests at that time • The requesting device samples its grant signal until the master is granted access. The master then initiates a data transfer between the master and a slave when the current bus master releases the bus • Arbitration mechanisms • Fixed priority, round-robin, hybrid

6. MicroBlaze Processor Bus Example CacheLink IIC IOPB Bus Ext Mem ILMB Bus UART IXCL GPIO Ext Mem BRAM ILMB IOPB MicroBlaze™ Ethernet DLMB DOPB DXCL LCD DLMB Bus DOPB Bus Ext Mem BRAM CacheLink INTC All buses are 32 bits OPB ARB

7. CoreConnect Bus Architecture • The IBM CoreConnect bus architecture standard provides three buses for interconnecting cores, library macros, and custom logic: • Processor Local Bus (PLB) • On-Chip Peripheral Bus (OPB) • Device Control Register (DCR) bus • IBM offers a no-fee, royalty-free CoreConnect bus architecture license • Licenses receive the PLB arbiter, OPB arbiter, and PLB/OPB bridge designs along with bus-model toolkits and bus-functional compilers for the PLB, OPB, and DCR buses • Required only if you create your own CoreConnect bus architecture peripheral or you are using the Bus Functional Model (BFM)

8. Outline • Buses 101: Arbiter, Master, Slave • On-Chip Peripheral Bus (OPB) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations • PowerPC Processor Programmer’s Model • Reset Logicin the PowerPC Processor • JTAG Configurations in the Virtex-II Pro Device

9. On-Chip Peripheral Bus (OPB) • The On-Chip Processor Bus (OPB) decouples lower bandwidth devices from the PLB • It is a less complex protocol than the PLB • No split transaction or address pipelining capability • Centralized bus arbitration—OPB arbiter • Connection infrastructure for the master and slave peripheral devices • The OPB bus is designed to alleviate system performance bottlenecks by reducing capacitive loading on the PLB • Fully synchronous to one clock • Shared 32-bit address bus; shared 32-bit data bus • Supports single-cycle data transfers among the master and the slaves • Supports multiple masters, determined by arbitration implementation • The bridge function can be the master on the PLB or OPB

10. On-Chip Peripheral Bus (OPB) • Supports 16 masters and an unlimited number of slaves (only limited by the expected performance) • The OPB arbiter receives bus requests from the OPB masters and grants the bus to one of them • Fixed and dynamic (LRU) priorities • Bus logic is implemented with AND-OR logic. Inactive devices drive zeros • Read and write data buses can be separated to reduce loading on the OPB_DBus signal

11. Outline • Buses 101: Arbiter, Master, Slave • On-Chip Peripheral Bus (OPB) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations • PowerPC Processor Programmer’s Model • Reset Logicin the PowerPC Processor • JTAG Configurations in the Virtex-II Pro Device

12. Local Memory Bus (LMB) • The Local Memory Bus (LMB) provides single-cycle access to on-chip dual-port block RAM for MicroBlaze™ processors • The LMB provides simple synchronous protocol for efficient block RAM transfers • The LMB provides maximum guaranteed performance of 125 MHz in Virtex-II devices for the local memory subsystem • DLMB: Data interface, local memory bus (block RAM only) • ILMB: Instruction interface, local memory bus (block RAM only)

13. LMB Timing • Rules for generating an LMB clock • The MB, LMB, and OPB clock must be the same clock • Use timing constraints to determine the clock speed

14. Bus Summary

15. Bus Summary

16. Outline • Buses 101: Arbiter, Master, Slave • Processor Local Bus (PLB) • On-Chip Peripheral Bus (OPB) • Device Control Register (DCR) • On-Chip Memory Bus (OCM) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations • PowerPC Processor Programmer’s Model • Reset Logicin the PowerPC Processor • JTAG Configurations in the Virtex-II Pro Device

17. The Software Streaming Data Challenge • Suppose you want to move data through a hardware/software processing application with following characteristics • Data may be of a streaming or burst nature • Deterministic latency between hardware and software • Possible solutions include • Bus peripheral, maybe OPB • Multiple clock-cycle overhead • Address decode time • Arbitration, loss of hardware/software coherency • Custom microprocessor instruction access to peripheral hardware • May require processor to be stalled • Complex logic can slow overall processor speed • May require assembly language to access special instruction • Fast Simplex Links (see next slide)

18. MicroBlaze 32-Bit RISC Core OPB On-Chip Peripheral Bus Arbiter Custom Functions Custom Functions Memory Controller 10/100 E-Net UART MicroBlaze Processor-Based Embedded Design I-Cache BRAM Local Memory Bus Flexible Soft IP BRAM Configurable Sizes D-Cache BRAM Possible in Virtex™-II Pro Fast Simplex Link 0,1….7 Off-Chip Memory FLASH/SRAM FSL Channels

19. FIFO 32-bit data Another Alternative: Fast Simplex Links ( FSL) • Unidirectional point-to-point FIFO-based communication • Dedicated (unshared) and nonarbitrated architecture • Dedicated MicroBlaze™ C and ASM instructions for easy access • High speed, access in as little as two clocks on processor side, 600 MHz at hardware interface • Available in Xilinx Platform Studio (XPS) as a bus interface library core from Hardware → Create or Import Peripheral Wizard FSL_M_Clk FSL_S_Clk FSL_M_Data [0:31] FSL_S_Data [0:31] FSL_M_Control FSL_S_Control FSL_M_Write FSL_S_Read FSL_M_Full FSL_S_Exists FIFO Depth

20. FSL Advantages • It is simple, fast, and easy to use • FSL versus Custom uP instruction • Custom hardware is not dependent on instruction decode • Clock speed is not slowed down by new hardware • FSL is faster than a bus interface – saves clock cycles • Eliminates bus signaling overhead • No arbitration • No address decode • No acknowledge cycles • Decoupled data clock from CPU allows for asynchronous operation • Minimal FPGA fabric overhead • No need to stall the processor because of custom function clock latency • No need to modify the C compiler (could be risky!) • Control bits limit the need for a complex interrupt structure

21. FSL Highlights • FSL architecture is automatically generated based on user requirements . Required resources from 21 to 451 slices • Core can be configured as master or slave • Separate control bit channel • MicroBlaze™ allows for up to eight parallel FSL channels • Easy to use C calls for MicroBlaze • Predefine compiler functions • Optional use of assembler language

22. FSL Features • Configurable data bus widths – 8, 16, 32 bits • Configurable FIFO depths – 1 to 8193 using SRL16 or block RAM • Synchronous or asynchronous FIFO clocking with respect to the MicroBlaze™ system clock • Selectable use of control bit • Blocking and nonblocking software instructions for data and control (get and put) • Simple software interface using predefined C instructions; Automatically generated C drivers

23. Knowledge Check • Which buses are included in the CoreConnect bus architecture standard? • What is the maximum performance of the LMB in a Virtex™-II device?

24. Answers • Which buses are included in the CoreConnect bus architecture standard? • PLB, OPB, and DCR • What is the maximum performance of the LMB in a Virtex™-II device? • 125 MHz

25. Knowledge Check • What is FSL? • How many FSL channels are supported by • MicroBlaze • How FSL can improve performance?

26. Answers • What is FSL? • FSL is a dedicated simplex link with a FIFO interface • How many FSL channels are supported by • MicroBlaze 8 • How FSL can improve performance? • Since FSL is a dedicated link bus arbitration does not exist. Fixed data latency of two clocks assuming data is available

27. Outline • Buses 101: Arbiter, Master, Slave • Processor Local Bus (PLB) • On-Chip Peripheral Bus (OPB) • Device Control Register (DCR) • On-Chip Memory Bus (OCM) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations • PowerPC Processor Programmer’s Model • Reset Logicin the PowerPC Processor • JTAG Configurations in the Virtex-II Pro Device

28. MicroBlaze Processor • Embedded soft RISC processor (version 4.00a) • 32-bit address and data busses • 32-bit instruction word (three operands and two addressing modes) • 32 registers (32-bit wide) • 3 pipe stages (single issue) • Big-endian format • Buses • Full Harvard-architecture • OPB (CoreConnect bus architecture standard), instruction, and data • LMB for connecting to local block RAM (faster), instruction, and data • Fast Simplex Links: Dedicated unidirectional point-to-point data streaming interfaces • Dedicated CacheLink ports for instruction and data caching with four-words cache line size and critical word first access capability

29. MicroBlaze Processor • ALU • Uses hardware multipliers/DSP48 in the Virtex™-II or later families • Barrel shifter • Floating Point Unit • Implements IEEE 754 single precision floating point standards • Supports addition, subtraction, multiplication, division, and comparision • Program counter • Instruction decode • Instruction cache • Direct-mapped • Configurable caching over OPB or CacheLink • Configurable size: 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB

30. MicroBlaze Processor Performance • All instruction takes one clock cycle, except: • Load and store (two clock cycles) • Multiply (two clock cycles) • Branches (three clock cycles, can be one clock cycle) • Operating Frequency • 180 MHz on Virtex-4 LX (-12) devices • 150 MHz on Virtex-II Pro (-7) devices • 100 MHz on Spartan 3 (-5) devices • Dhrystone-MIPs (2.1 standard benchmark) using LMB block RAM • 166 MHz on Virtex-4 LX (-12) devices • 138 MHz on Virtex-II Pro (-7) devices • 92 MHz on Spartan 3 (-5) devices • Peak performance of 0.92 DIMPS/MHz • 1269 LUTs in Virtex-4, 1225 LUTS in Virtex-II Pro, 1318 LUTs in Spartan 3

31. 0xFFFF_FFFF Peripherals OPB Memory LMB Memory Reserved 0x0000_004F 0x0000_0028 Hardware Exception 0x0000_0020 Break 0x0000_0018 Interrupt Address 0x0000_0010 Exception Address 0x0000_0008 Reset Address 0x0000_0000 MicroBlaze Processor Memory Space • Memory and peripherals • The MicroBlaze processor uses 32-bit addresses • Special addresses • MicroBlaze processors must have user-writable memory from 0x00000000 through 0x0000004F • Each vector consists of two instructions IMM followed by a BRAI instruction to address full memory range

32. Outline • Buses 101: Arbiter, Master, Slave • Processor Local Bus (PLB) • On-Chip Peripheral Bus (OPB) • Device Control Register (DCR) • On-Chip Memory Bus (OCM) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations

33. Bus Configuration Systems

34. Outline • Buses 101: Arbiter, Master, Slave • Processor Local Bus (PLB) • On-Chip Peripheral Bus (OPB) • Device Control Register (DCR) • On-Chip Memory Bus (OCM) • Local Memory Bus (LMB) • Fast Simplex Links (FSL) • MicroBlaze Processor Programmer’s Model • MicroBlaze Processor Configurations

35. Knowledge Check Where do the following vectors reside in the MicroBlaze processor? • Reset • Interrupt • Exception • What is the starting address of the code if LMB memory is present?

36. Answers • Where do the following vectors reside in the MicroBlaze processor? • Reset (0x00000000) • Interrupt (0x00000010) • Exception (0x00000008) • What is the starting address of the code if LMB memory is present? • 0x00000050

37. Where Can I Learn More? • Tool documentation • Processor IP Reference Guide • Processor documentation • MicroBlaze™ Processor Reference Guide • Support Website • EDK Website: www.xilinx.com/edk