ITRS Conference 12-14 July 2004 San Francisco, California

1. ITRS Conference 12-14 July 2004 San Francisco, California 2004 ITRSYield Enhancement (YE) Update

2. Yield Enhancement Presentation Outline • ITWG Co-chairs and Contributors • Yield Enhancement Definition and Scope • Difficult Challenges • Proposed Revision Areas for 2004 and 2005 • Yield Model and Defect Budget (YMDB) • Defect Detection and Characterization (DDC) • Yield Learning (YL) • Wafer Environment Contamination Control (WECC) • Summary

3. Taiwan Tings Wang Promos Technologies Len Mei Promos Technologies United States Fred Lakhani Sematech Kevin Pate Intel 2004 ITRS YE ITWG Co-chairs • Europe • Ines Thurner • Infineon • Japan • Masahiko Ikeno • Renesas • Yuichiro Yamazaki • Toshiba • Korea • TBD Note: Contributions of all TWG members around the world are gratefully acknowledged.

4. Europe Ines Thurner (Infineon) Lothar Pfitzner (FhG-IISB) Andreas Nutsch (FhG-IISB) Andreas Neuber (M+W Zander) Hans-Martin Dudenhausen (isiltec) Dieter Rathei (austriamicrosystems) Japan Masahiko Ikeno (Renesas) Yuichiro Yamazaki (Toshiba) Hiroshi Kitajima (Selete) Eiichi Kawamura (Fujitsu) Fujii Shinji (Matsushita) Sumio Kuwabara (NEC EL) Akira Okamoto (Sony) Takanori Ozawa (Rohm) Ken Tsugane (Hitachi) Fumio Mizuno (Meisei Univ.) Masakuzu Ichikawa (Univ.of Tokyo) Isao Kojima (AIST) Kazuo Nishihagi (Technos) Yoji Ichiyasu (Hitachi-HT) United States Fred Lakhani (ISMT) Christopher Long (IBM) Kevin Pate (Intel) John Kurowski (IBM) Chris Muller (Purafil) Mike Retersdorf (AMD) Ron Remke (ISMT) Mike McIntyre (AMD) Rick Jarvis (AMD) Ken Tobin (ORNL) Hank Walker (Texas A&M) Ralph Richardson (Air Products) Mark Camenzind (Air Liquide) Joe O’Sullivan (Intel) John DeGenova (TI) Jeff Chapman (IBM) Val Stradzs (Intel) Keith Kerwin (TI) James McAndrew (Air Liquide) Billy Jones (Infineon) Bob McDonald (Metara) Kristen Cavicci (BOCE) Tony Schleisman (Air Liquide) Bart Tillotson (Arch) Tracey Boswell (Sematech) 2004 YE ITWG Contributors • Taiwan • Tings Wang (Promos Tech) • Len Mei (Promos Tech) • Steven Ma (Mxic) • Jimmy Tseng (PSC) • CH Chang (SIS) • Chan-Yuan Chen (TSMC) • Jim Huang (UMC) • CS Yang (Winbond)

5. Yield Enhancement Definition and Scope • Definition: • To improve the baseline yield for a given technology node from R&D yield level to mature yield. • The definition assumes a functional baseline process for a given process technology and its compatibility with the design of the product being fabricated. • The definition reinforces the chapter focus on the yield ramp portion of the yield learning curve. • Scope • Limit scope of YE chapter to wafer sort yield. • Fab line yield, assembly/packaging yield, and final test yield are not included in the scope of the YE chapter.

6. Difficult Challenges • High-Aspect-Ratio Inspection • High-speed, cost-effective tools are needed to rapidly detect defects at 1/2 X ground rule (GR) associated with high-aspect-ratio contacts, vias, and trenches and especially defects near or at the bottoms of these features. • Design for Manufacture & Test (DFM & DFT) • IC designs must be optimized for a given process capability and must be testable and diagnosable • Systematic Mechanisms Limited Yield (SMLY) -- Understanding SMLY is mandatory for achieving historic yield ramps in the future. • Data Management and Test Structures for Rapid Yield Learning • Automated, intelligent test structures, analysis and reduction algorithms that correlate facility, design, process, test, and work-in-process (WIP) data must be developed to enable the rapid root-cause analysis of yield-limiting conditions.

7. Difficult Challenges (continued) • Correlation of Impurity Level to Yield • Data, test structures, and methods are needed for correlating process fluid contamination types and levels to yield and determine required control limits • Relative importance of different contaminants to wafer yield • Yield Models • Random, systematic, parametric, and memory redundancy models must be developed and validated to correlate process-induced defects (PID), particle counts per wafer pass (PWP), and in-situ tool/process measurements to yield. • Detection of Ever-Shrinking Yield Critical Defects • High throughput, cost-effective, high capture rate detection tools are needed for ever-shrinking critical defects of interest • Non-visual Defect Detection -- In-line and end-of-line tools and techniques are needed to detect non-visual defects. • Wafer inspection of backside, bevel, edge, nanotopography and geometry

8. Proposed Revision Areas for 2004 & 2005 • Yield Model and Defect Budgets • New defect budget survey required for 2005 revision • Standardize yield model between FEP/Starting Materials and Yield Enhancement • Defect Detection and Characterization • Edge exclusion value is being aligned between YE, FEP, Litho, and Factory Integration • Developed Cost of Ownership model for patterned wafer inspection • Verify throughput capability for E-beam defect inspection tools • Yield Learning • Yield ramp-up becoming more important and targets need to be revised • Yield learning in this version depends on number of cycles per year. In future, this will be changed to wafer volume dependent model.

9. Proposed Revision Areas for 2004 & 2005 (cont.) • Wafer Environment Contamination Control • Air AMC: Will add requirements for acid control in litho, and acids & bases control in reticle storage • UPW: Based on benchmarking, silica and dissolved oxygen targets revised • Liquid Chems: On-line liquid particle counter sensitivity needs to be improved • Liquid Chems: Precursor, CMP, plating chemicals purity parameters are being established • Liquid Chems & Gases: Alignment of SEMI specs and standards with ITRS targets is in progress

10. Summary • The Yield Enhancement chapter revision for the 2004 ITRS roadmap is well underway. The following regions are taking the lead in revising various sections of the Yield Enhancement chapter: • Yield Model and Defect Budget Japan • Defect Detection and Characterization Europe • Yield Learning Taiwan • Wafer Environment Contamination Control USA • Smaller feature sizes, novel device structures, and new materials will continue to challenge yield enhancement methodologies