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SODA: A Low-power Architecture For Software Radio

SODA: A Low-power Architecture For Software Radio. Yuan Lin 1 , Hyunseok Lee 1 , Mark Woh 1 , Yoav Harel 1 , Scott Mahlke 1 , Trevor Mudge 1 , Chaitali Chakrabarti 2 , Krisztian Flautner 3 1 Advanced Computer Architecture Lab, University of Michigan

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SODA: A Low-power Architecture For Software Radio

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  1. SODA: A Low-power Architecture For Software Radio Yuan Lin1, Hyunseok Lee1, Mark Woh1, Yoav Harel1, Scott Mahlke1, Trevor Mudge1, Chaitali Chakrabarti2, Krisztian Flautner3 1Advanced Computer Architecture Lab, University of Michigan 2Department of Electrical Engineering, Arizona State University 3ARM, Ltd. 1

  2. Anatomy of 3G Cellular Phone 2

  3. Advantages of Software Defined Radio • Multi-mode operations • Lower costs • Faster time to market • Prototyping and bug fixes • Chip volumes • Longevity of platforms • Protocol complexity favors software dominated solutions • Enables future wireless communication innovations • Cognitive radio 3

  4. Why is SDR Challenging? • SDR Design Objectives for 3G and WiFi • Throughput requirements • 40Gops peak throughput • Power budget • 100mW~500mW peak power 4

  5. The Anatomy of Wireless Protocols 1. Filtering: suppress signals outside frequency band 2. Modulation: map source information onto signal waveforms 3. Channel Estimation: Estimate channel condition for transceivers 4. Error Correction: correct errors induced by noisy channel 5

  6. SDR – Application Specific Design • Wireless protocols are systems of DSP algorithms • System-level • Example: Specification of W-CDMA DCH channel • Algorithm-level • Example: Implementation of a 64 point FFT 6

  7. System Level Design Decisions 7

  8. SODA System Architecture • 4 PEs • static kernel mapping and scheduling • SIMD+Scalar units • 1 ARM GPP controller • scalar algorithms and protocol controls 8

  9. SODA Memory Organization • 2-Level scratchpad memories • 12KB Local scratchpad memory for stream queues • 64KB global scratchpad memory for large buffers • Low-throughput shared bus • 200MHz 32-bit bus • inter-PE communication using DMA 9

  10. DSP Algorithm Characteristics • 8 to 16-bit precision • Vector operations • long vectors • constant vector size • Static data movement patterns • Scalar operations 10

  11. SODA PE Architecture 11

  12. SODA PE SIMD Pipeline 12

  13. SODA PE SIMD Pipeline 13

  14. SODA PE SIMD Shuffle Network 14

  15. SODA PE Scalar Pipeline 15

  16. W-CDMA Mapping On SODA 16

  17. SDR Performance Distribution • 802.11a has higher number of total computational cycles • W-CDMA requires higher computational cycles per bit 17

  18. Power Consumption at 180nm • Wide SIMD requires higher number of pipeline registers • 802.11a consumes higher power than W-CDMA • 8-bit W-CDMA computation versus 16-bit 802.11a computation 18

  19. Summary • Key features of SODA • Multi-PE with scratchpad memories • Low throughput shared bus • 2-issue LIW: SIMD+(Scalar or AGU) • 32-wide SIMD processing • SIMD shuffle network 19

  20. Conclusion & Future Work • Conclusion • 2G and 3G SDR solutions are achievable in 90nm • Optimization opportunities at the algorithm, software and hardware levels • Future Work • SDR for Idle mode operation (ISLPED ’06) • SODA for 4G protocols • Application-specific language for SDR • Compiler for SODA 20

  21. Questions? • www.eecs.umich.edu/~sdrg 21

  22. Backup Slides 22

  23. Different Levels of Software Radio <source:http://www.sdrforum.org> 23

  24. Power Methodology • Our flow sequence was • Design Compiler and Silicon Ensemble • For Initial Floorplan Estimation • Physical Compiler • For placement and Optimization • Silicon Ensemble • Routing • We optimized for power and delay • Blocks like memory were generated with Artisan Memory Generators • We used the Synopsys IP Blocks as much as possible to get better compiled blocks 24

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