Deep Submicron CAD tools

1. Deep Submicron CAD tools 1998. 5. 19 조 준 동 SungKyunKwan Univ.

2. Capability of Tools SungKyunKwan Univ.

3. More Changes in Design Flow • The complexity and interactivity of the logic and physical design implementation phases requires more changes in the design flows. A number of EDA and ASIC companies are starting to advocate new methodologies for the whole area of clock and power distribution. The latest methodologies tend towards early development of the clock system, using chip location and loading as the key drivers for the clock design. After the basic clocking scheme is developed and the first pass parasitic parameters are extracted, then the rest of the circuitry is synthesized and routed. At this point, the first of the iterations for speed and power optimization is started. Area is no longer one of the driving issues, because a majority of the area is now fixed and dedicated to the logic and interconnections. Any changes in the clocking will be in the direction of trading off area for increased speed with little change in total power consumption. • According to Cadence's Tom Katsioulas, current technologies and methodologies are geared for a little automation and a lot of manual intervention. "The low amount of automation is a result of things like the number of gates (less than 50k); and the number of bits in the bus has been fairly small (eight or 16), so a lot of lines don't switch at the same time. Today clock trees are designed in pieces. Especially for large chips with multiple clocks, the tools generate one clock per block. They start with largest block with the most loads, which generates the maximum delays, then match other blocks [automatically with minimal constraints]." SungKyunKwan Univ.

4. Hierarchical Design System • Today:The system design engineers were now able to design semi-custom silicon chips. Initially the library at the system level contained only gate level models for simulation. The ASIC suppliers did the actual physical chip layout and chip fabrication. Foundry customers became more sophisticated. Physical library cells and abstractions of the technology file were added to the system level library. As the EDA tools at each level evolved to a richer set of functionality, more abstract information from the lower library was needed. • Future: SEMATECH proposes that a "System on Silicon" design system must be hierarchical. Each library level will be an abstraction of the more detailed library level information from the library below it. One very interesting piece of information needs to be abstracted up to every level: interconnect parasitic information as a timing delay parameter. A floor planner is required at the architectural level. Floor planning is important because of timing delay and a realizable layout. The system level design team cannot wait for floor planning to be done at the Gate Level design; that's too late. Change in the floor plan not only affects pin placement and net lengths. It also affects logic partitioning that may affect the system architecture. The design systems of the future must account for interconnect parasitics at every level. SungKyunKwan Univ.

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6. IC Design System • The IC design system for the deep submicron era is going to look very similar to the system of today. Next-generation tools will have added features as well as the introduction of new tools. The development or requirements of these EDA tools will be driven by the new problems created by deep submicron. The biggest dilemma is understanding what these problems are. IC designers must begin with the lower level primitive models such as devices, passive components and interconnect. All other higher level models are derived from these primitive models. Based on previous design experience and these new models the design engineers will be able to anticipate many of the new problems they will need to solve. Due to the fact certain lateral dimensions are less than the vertical dimensions, the traditional method of empirical measurements for models will become nearly impossible or very inaccurate. The design team needs to get closer to the physics. They need access to other tools to help understand the effects of the laws of physics in the deep submicron era. The least understood models are interconnect parasitics, particularly capacitance. Interconnect parasitics affect the timing delay between active devices or blocks. SungKyunKwan Univ.

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8. EDA Industry Focus • The EDA industry focus has been on four key areas: design entry, simulation, physical layout and layout verification. Layout verification emphasized DRC (design rule checking) and LVS (layout vs. schematic). All EDA tools require information from the technology file supplied by the user. • LPE: The EDA industry has supplied many tools to help the Design Community solve many of the problems. One of the remaining problems is interconnect parasitics. EDA vendors have provided the design community with LPE (layout parameter extraction) capability for more than a decade, but this capability has not been widely used. What has been the impediment? The problem was the development of accurate models, particularly capacitance. • Parallel plate was too simple; redesign was the workaround. • Empirical measurements were expensive and usually produced insufficient information. • In-house development of 2D and 3D solvers is very expensive and generally not affordable. • Remember, EDA tools are a part of a knowledge base design system. The knowledge (models) for interconnect parasitics found in the technology library is supplied by the design team. SungKyunKwan Univ.

9. Capacitance Models have been ignored • Interconnect parasitic capacitance has generally been ignored for quite a few years. Everyone tends to assume that accurate interconnect parasitic models should be as prevalent and available as accurate transistor models are today. This is not the case. Accuracy is also a relative term. The level of accuracy depends upon what is needed. All models used by the design community tend to be abstractions of more accurate models. The level of accuracy is dictated by the application of the model and the tradeoffs of simulation time, hardware resources, the control tolerances on the process parameters and the final impact on performance. The knowledge for determining what is needed depends upon the experience base of the design community. This is the crux of the problem. The design community has generally ignored this problem, and with good reason: no compelling event justified the effort. Circumstances have now changed that need. The advent of deep submicron and the need for a competitive edge requires the design community to address this problem, and to develop that experience base as quickly as possible. The lowest cost method is to produce this information through simulation, which means returning to the fundamentals of physics. SungKyunKwan Univ.

10. Testimonials • "We have used Raphael to characterize the interconnects for our 1Mbit SMART CACHE SRAM design. This chip is designed using 0.35mm four-layer metal technology, and the maximum speed demonstrated is 294 Mhz at room temperature. Because of the accuracy delivered by Raphael, the design team was able to reduce the design margin from the typical 30 percent to between 5 percent and 10 percent. We are very happy with the chip performance and we would like to thank TMA for the contributions from Raphael." • Ken Lee, Ph.D. Principal Project Engineer, Hewlett-Packard Laboratories • "Hewlett-Packard has been using TMA's Raphael to characterize the interconnect structures and generate interconnect models for many high-speed digital IC designs. Data points have shown the difference between Raphael simulation results and the real measurements is within 5 percent accuracy. We have strong confidence in using Raphael to characterize the interconnects for Hewlett-Packard's advanced CMOS technologies, since Raphael has contributed to many IC design successes at HP." • Keh-Jeng Chang, Ph.D. • Member of Technical Staff - Integrated Circuit Business Division • Hewlett-Packard Company -- Winston Jung, TMA SungKyunKwan Univ.

11. DASYS • Synthesis tools must improve interconnect delays • Today's synthesis tools do a poor job of estimating the interconnect wiring delay, which accounts for up to 70% of the total delay in deep submicron geometries. When the designer finally gets the real delay information back from physical layout, he very likely has many timing problems resulting in a non-functional circuit. • RapidPath solves this problem by shortening the time spent in logic synthesis and layout by a factor of 5X to 10X, taking the design from a behavioral description through layout in hours, negating the need to use estimated interconnect delay data for timing analysis. RapidPath produces real delay data from layout, revealing the actual timing performance of the chip, allowing the designer to make changes that affect the timing -- and die size and power -- at the behavioral level. SungKyunKwan Univ.

12. DASYS • Partitioning produces fast path to layout by utilizing best downstream tools. • RapidPath partitions the design into control, datapath, memory and random logic. It then invokes the best downstream tool to work on the partitioned portions. The controller and random logic is sent to logic synthesis, the datapath is sent to a datapath compiler tool, and memory is sent to a memory compiler. • Current behavioral synthesis tools force the entire design through bit-oriented logic synthesis tools, which lose the concept of the word-oriented datapath. The highly regular and structured datapath elements are treated as random logic by logic synthesis, resulting in loss of bit grouping, longer interconnect wiring that produces longer delays, excessive skew, and larger die sizes. Forcing 100% of the design through logic synthesis also produces excessively long synthesis times, and in some cases the synthesis process never reaches completion. The synthesis tool hands off the design to floorplanning and place and route as standard cells only, producing very long place and route times. SungKyunKwan Univ.

13. DASYS • 3X to 4X Reduction in Overall Design Cycle • RapidPath reduces the logic synthesis and physical layout times by a factor of 5X to 10X. This results in an overall design cycle reduction of 3X to 4X. At Delco, designers were able to accomplish in three weeks what took them one year by hand. The RapidPath-synthesized result matched the quality of manual design, and the designers gained the advantages of behavioral synthesis -- ease of debugging and ease of design extension. • Smaller Die Sizes, Faster Performance • RapidPath partitions the datapath and controllers to create blocks that are ready to be floorplanned and hierarchically placed and routed. By controlling the aspect ratios and the interconnect into and out of blocks, RapidPath creates designs that will pack and route easily during physical design. • RapidPath partitions the datapaths and controllers to manage aspect ratios and interconnect. Where it makes sense, RapidPath will partition out a small portion of the main controller block to be closely physically associated with its corresponding datapath block. SungKyunKwan Univ.

14. High Level Design System, LSI LogicTeam On Deep-Submicron IC Design • High Level Design Systems, Inc. is the leading supplier of IC floorplanning tools for complex submicron gate-array and cell-based integrated circuit designs, and is a leader in the emerging market for deep-submicron IC-design tools. The company's design-planning tools link the RTL, logic and physical IC-design phases to enable the creation of smaller, denser ICs on critical time-to-market schedules and include Top-Down Design Planner for RTL design, Logic Design Planner?for logic design, and Physical Design Planner?for physical layout. HLDS Inc. is publicly traded on the Vancouver Stock Exchange. Complete information on the company and its products is available at http://www.hlds.com. • LSI Logic Corporation (NYSE: LSI), the System on a Chip Company, is a leading supplier of custom high-performance semiconductors, with operations worldwide. The company enables customers to build complete systems on a single chip with its CoreWare design program, thereby increasing performance, lowering system costs and accelerating time to market. LSI Logic develops application-optimized products in partnership with trendsetting customers, and operates leading-edge high-volume manufacturing facilities to produce submicron chips. The company maintains a high level of quality, as demonstrated by its ISO 9000 certifications. LSI Logic is headquartered at 1551 McCarthy Blvd., Milpitas, California 95035, (408) 433-8000, http://www.lsilogic.com. SungKyunKwan Univ.

15. Floorplan Manager(Synopsys) • Reduces costly post-layout timing violations by reoptimizing critical paths based on physical information • Increases timing performance by accurately calculating interconnect delays based on cell placement information • Accelerates tapeout faster by design convergence between the logical and physical implementation • Post-layout timing violations in high-performance, submicron designs can frequently add weeks and even months to your project schedules. Costly layout-related design iterations are due primarily to: • A mismatch between the logical (pre-layout) and physical (post-layout) hierarchy. This occurs because there is no means for physical design information to be taken into consideration at the front end of the design cycle, during synthesis. • Statistical wireload models are inaccurate for modeling net delays in deep-submicron designs. SungKyunKwan Univ.