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Progettazione di circuiti e sistemi VLSI

Progettazione di circuiti e sistemi VLSI. Anno Accademico 2010-2011 Lezione 11 5.5.11 Memorie ( vedi anche i file pcs1_memorie.pdf pcs2_memorie.pdf – pcs3_memorie.pdf ). Chapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability

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Progettazione di circuiti e sistemi VLSI

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  1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 11 5.5.11 Memorie (vedi anche i file pcs1_memorie.pdf pcs2_memorie.pdf – pcs3_memorie.pdf ) Sistemi Elettronici Programmabili

  2. Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability • Case Studies Sistemi Elettronici Programmabili

  3. Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM Sistemi Elettronici Programmabili

  4. Memory Timing: Definitions Sistemi Elettronici Programmabili

  5. Decoder reduces the number of select signals K = log N 2 Memory Architecture: Decoders M bits M bits S S 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A cell cell 1 words A N -1 K Decoder S N -2 - Word N 2 Word N 2 - S N - - -1 Word N 1 Word N 1 K log N = 2 Input-Output Input-Output ( M bits) ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Sistemi Elettronici Programmabili

  6. Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2L-K - Amplify swing to rail-to-rail amplitude Selects appropriate word Sistemi Elettronici Programmabili

  7. Data (64 bits) I/O Buffers Comparand Mask Commands CAM Array R/W Address (9 bits) Control Logic 9 2 words 3 64 bits Validity Bits 9 2 Priority Encoder Address Decoder Contents-Addressable Memory I/O Buffers I/O Buffers Commands Commands Validity Bits 9 2 Priority Encoder Validity Bits Address Decoder 9 2 Priority Encoder Address Decoder Sistemi Elettronici Programmabili

  8. DRAM Timing SRAM Timing Self-timed Multiplexed Adressing Memory Timing: Approaches Sistemi Elettronici Programmabili

  9. Read-Only Memory Cells BL BL BL VDD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2 Sistemi Elettronici Programmabili

  10. MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads Sistemi Elettronici Programmabili

  11. MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] Sistemi Elettronici Programmabili

  12. MOS NOR ROM Layout Cell (9.5l x 7l) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Sistemi Elettronici Programmabili

  13. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row Sistemi Elettronici Programmabili

  14. No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM MOS NAND ROM Layout Cell (8l x 7l) Programmming using the Metal-1 Layer Only Polysilicon Diffusion Metal1 on Diffusion Sistemi Elettronici Programmabili

  15. V DD BL r word WL C bit c word Equivalent Transient Model for MOS NOR ROM Model for NOR ROM • Word line parasitics • Wire capacitance and gate capacitance • Wire resistance (polysilicon) • Bit line parasitics • Resistance not dominant (metal) • Drain and Gate-Drain capacitance Sistemi Elettronici Programmabili

  16. Equivalent Transient Model for MOS NAND ROM V DD Model for NAND ROM BL C L r bit c bit r word WL c word • Word line parasitics • Similar to NOR ROM • Bit line parasitics • Resistance of cascaded transistors dominates • Drain/Source and complete gate capacitance Sistemi Elettronici Programmabili

  17. D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section Sistemi Elettronici Programmabili

  18. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V -2.5 V - S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming Sistemi Elettronici Programmabili

  19. A “Programmable-Threshold” Transistor Sistemi Elettronici Programmabili

  20. FLOTOX EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim I-V characteristic FLOTOX transistor Sistemi Elettronici Programmabili

  21. V DD EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell Sistemi Elettronici Programmabili

  22. Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide 1 1 n source n drain programming p- substrate Many other options … Sistemi Elettronici Programmabili

  23. Basic Operations in a NOR Flash Memory:Erase Sistemi Elettronici Programmabili

  24. Basic Operations in a NOR Flash Memory:Write Sistemi Elettronici Programmabili

  25. Basic Operations in a NOR Flash Memory:Write Sistemi Elettronici Programmabili

  26. Basic Operations in a NOR Flash Memory:Read Sistemi Elettronici Programmabili

  27. NAND Flash Memory Word line(poly) Unit Cell Source line (Diff. Layer) Sistemi Elettronici Programmabili Courtesy Toshiba

  28. Select transistor Word lines Active area STI Bit line contact Source line contact NAND Flash Memory Courtesy Toshiba Sistemi Elettronici Programmabili

  29. Characteristics of State-of-the-art NVM Sistemi Elettronici Programmabili

  30. Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended Sistemi Elettronici Programmabili

  31. Q 6-transistor CMOS SRAM Cell WL V DD M M 2 4 Q M M 6 5 M M 1 3 BL BL Sistemi Elettronici Programmabili

  32. CMOS SRAM Analysis (Read) WL V DD M BL 4 BL Q 0 = M Q 1 = 6 M 5 V V V M DD DD DD 1 C C bit bit Sistemi Elettronici Programmabili

  33. CMOS SRAM Analysis (Read) 1.2 1 0.8 0.6 Voltage Rise (V) 0.4 0.2 Voltage rise [V] 0 0 0.5 1 1.2 1.5 2 2.5 3 Cell Ratio (CR) Sistemi Elettronici Programmabili

  34. WL V DD M 4 M Q 0 = 6 M 5 Q 1 = M 1 V DD BL 1 BL 0 = = CMOS SRAM Analysis (Write) Sistemi Elettronici Programmabili

  35. CMOS SRAM Analysis (Write) Sistemi Elettronici Programmabili

  36. Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2 Sistemi Elettronici Programmabili

  37. SRAM Characteristics Sistemi Elettronici Programmabili

  38. BL 1 BL 2 WWL WWL RWL RWL M 3 V V X M X 2 DD T 1 M 2 V DD BL 1 C S V D BL 2 V V 2 DD T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V -V WWL Tn 3-Transistor DRAM Cell Sistemi Elettronici Programmabili

  39. C S ------------ V V D = – V = V – V BL PRE BIT PRE C + C S BL 1-Transistor DRAM Cell Write: C is charged or discharged by asserting WL and BL. S Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV. Sistemi Elettronici Programmabili

  40. DRAM Cell Observations • 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. • DRAM memory cells are single ended in contrast to SRAM cells. • The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. • Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. • When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value thanVDD Sistemi Elettronici Programmabili

  41. Metal word line SiO 2 Poly Field Oxide Diffused + + n n bit line Inversion layer Poly Polysilicon induced by Polysilicon plate plate bias gate 1-T DRAM Cell Capacitor M word 1 line Cross-section Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area Sistemi Elettronici Programmabili

  42. Bit Bit Bit Bit Bit Bit Word M8 M9 M4 M5 CAM ••• CAM M6 M7 Word S S Word int CAM ••• CAM M3 M2 Match M1 Wired-NOR Match Line Static CAM Memory Cell ••• ••• Sistemi Elettronici Programmabili

  43. CAM in Cache Memory CAM SRAM ARRAY ARRAY Hit Logic Address Decoder Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data Sistemi Elettronici Programmabili

  44. Periphery • Decoders • Sense Amplifiers • Input/Output Buffers • Control / Timing Circuitry Sistemi Elettronici Programmabili

  45. Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder Sistemi Elettronici Programmabili

  46. Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL 0 A A A A A A A A A A A A A A A A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 0 0 1 3 2 2 3 Sistemi Elettronici Programmabili

  47. V DD V DD V DD V DD Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 V A A A A f DD 0 0 1 1 A A A A f 0 0 1 1 2-input NAND decoder 2-input NOR decoder Sistemi Elettronici Programmabili

  48. D make V as small × D C V as possible t = ---------------- p I av large small Sense Amplifiers Idea: Use Sense Amplifer small s.a. transition input output Sistemi Elettronici Programmabili

  49. Differential Sense Amplifier V DD M M 3 4 y Out M M bit bit 1 2 M SE 5 Directly applicable toSRAMs Sistemi Elettronici Programmabili

  50. Differential Sensing ― SRAM Sistemi Elettronici Programmabili

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