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IV. Basic Hardware, Arithmetic, ALU

IV. Basic Hardware, Arithmetic, ALU. operation. a. ALU. 32. result. 32. b. 32. Arithmetic. Where we've been: Performance (seconds, cycles, instructions) Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead:

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IV. Basic Hardware, Arithmetic, ALU

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  1. IV. Basic Hardware, Arithmetic, ALU

  2. operation a ALU 32 result 32 b 32 Arithmetic • Where we've been: • Performance (seconds, cycles, instructions) • Abstractions: Instruction Set Architecture Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture • Memory • Registers • ALU: central unit to compute arithmetic and logical operations • Buses and Connections • Control: fetching and decodingoperations, controlling the hardware

  3. Structure • Hardware Model, Basic Circuits • Notations, Numbers & Arithmetic • Addition/Subtraction • building a simple ALU • Multiplication/Division • Floating-Point

  4. Hardware Model Modular design • complex circuits are built from basic gates • abstraction levels • interfaces and functionality of modules are precisely specified • functionality should be verified or at least testet • top-down or bottom-up • performance and cost are important • estimate delay and cost of circuits by simple hardware model • relative to inverter delay and cost • additional issues: • minimum and maximum delays • fanout restrictions • wire delays

  5. Inverter Function Symbol Cost and Delay estimates Basic Gates

  6. Inverter AND-Gate Function Symbol Cost and Delay estimates Basic Gates

  7. Inverter AND-Gate NAND-Gate Function Symbol Cost and Delay estimates Basic Gates

  8. Inverter AND-Gate NAND-Gate OR-Gate Function Symbol Cost and Delay estimates Basic Gates

  9. Inverter AND-Gate NAND-Gate OR-Gate NOR-Gate Function Symbol Cost and Delay estimates Basic Gates

  10. Inverter AND-Gate NAND-Gate OR-Gate NOR-Gate XOR-Gate Function Symbol Cost and Delay estimates Basic Gates

  11. Inverter AND-Gate NAND-Gate OR-Gate NOR-Gate XOR-Gate XNOR-Gate Function Symbol Cost and Delay estimates Basic Gates

  12. Inverter AND-Gate NAND-Gate OR-Gate NOR-Gate XOR-Gate XNOR-Gate MUX (Multiplexer) Function Symbol Cost and Delay estimates Basic Gates

  13. Inverter AND-Gate NAND-Gate OR-Gate NOR-Gate XOR-Gate XNOR-Gate MUX (Multiplexer) Tristate-Driver Function Symbol Cost and Delay estimates Basic Gates

  14. Combinational circuits: network consisting of basic gates (no memory) signals propagate from inputs to outputs (no cycles in paths) cost: accumulated cost of basic gates delay: maximum delay on a path from inputs to outputs Examples: Combinational Circuits

  15. Problems: exponential growth of complexity with input size n even specification is complicated correctness in first iteration verification, test very important at each abstraction level Formal methods for verification become more important Verification during design modular design well defined interfaces and functionality in the following: definition of number types and representations for specification Combinational Circuits

  16. Numbers • Bits are just bits (0 or 1, no inherent meaning) conventions define relationship between bits and numbers • distinction between number value <---> number representation five • focus: binary numbers (base 2) with a fixed length n 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...represent values: 0 … 2n-1

  17. Numbers • problems with binary numbers of fixed length numbers are finite • overflow in arithmetic operations fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) • How do we represent negative numbers? bit strings of fixed length • available bit patterns stay the same i.e., which bit patterns will represent which numbers? Examples: • One’s complement representation • Two’s complement representation • Sign magnitude representation

  18. Possible Representations • Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations • Which one is best?

  19. MIPS • 32 bit signed numbers (two’s complement):0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

  20. Notation Bit strings: sequences of bits (concatenation also by (..,..,..) ) a= 0011010 = (001,10,10) For bit and natural numbers n : : string consisting of n copies of x Bits of strings are indexed from right (0) to left (n-1): or

  21. Binary representation Natural number with binary representation :

  22. Binary representation Natural number with binary representation : Range of numbers which have a binary representation of length n :

  23. Binary representation Natural number with binary representation : Range of numbers which have a binary representation of length n : n -bit binary representation of a natural number : with

  24. Two’s complement representation Natural number with two’s complement representation :

  25. Two’s complement representation Natural number with two’s complement representation : Range of numbers with two’s complement representation of length n :

  26. Two’s complement representation Natural number with two’s complement representation : Range of numbers with two’s complement representation of length n : n -bit two’s complement representation of a natural number : with

  27. Basic properties For : • leading zeros do not change the value of a binary representation

  28. Basic properties For : • leading zeros do not change the value of a binary representation • binary representations can be split for each

  29. Basic properties For : • leading zeros do not change the value of a binary representation • binary representations can be split for each • two’s complement representations have a sign bit a[n-1] :

  30. Basic properties For : • leading zeros do not change the value of a binary representation • binary representations can be split for each • two’s complement representations have a sign bit a[n-1] :

  31. Basic properties For : • leading zeros do not change the value of a binary representation • binary representations can be split for each • two’s complement representations have a sign bit a[n-1] : • construct two’s complement representation from binary representation:

  32. Basic properties For : • leading zeros do not change the value of a binary representation • binary representations can be split for each • two’s complement representations have a sign bit a[n-1] : • construct two’s complement representation from binary representation:note, that two’s complement representation is longer by one bit

  33. Basic properties(2) For : • sign extension does not change the value

  34. Basic properties(2) For : • sign extension does not change the value • negation of a number in two’s complement representation

  35. Basic properties(2) For : • sign extension does not change the value • negation of a number in two’s complement representationbasis for subtraction algorithm !

  36. Basic properties(2) For : • sign extension does not change the value • negation of a number in two’s complement representationbasis for subtraction algorithm ! • congruencies modulo , :

  37. Basic properties(3) • Two’s complement addition based on binary addition: For : the result of the n -bit binary addition is useful for n -bit two’s complement addition:

  38. Examples Let a= a[7:0]= 10101110

  39. Examples Let a= a[7:0]= 10101110

  40. Example (binary composition) Let a= a[7:0]= 10101110

  41. Example (sign extension) Let a= a[4:0]= 01110, b=b[4:0]=10100

  42. Example (two’s complement negation) Let a= a[4:0]= 01110

  43. Example (two’s complement negation) Let a= a[4:0]= 01110

  44. Example (bin&2’s compl. addition) Let a= a[4:0]= 00110, b=b[4:0]=10000 note: exact addition result might require one more bit !

  45. Summary Notation & number representations • Important to consider for two’s complement and binary represent. : • range of the numbers ! • leading zeros • sign extensions (two’s complement) • Addition/Subtraction based on • Negation of numbers in two’s complement representation • inversion • increment • Subtraction by addition of negative values (two’s complement) • Use of binary addition hardware for two’s complement addition

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