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TIMER INTERFACE MODULE (TIM)

TIMER INTERFACE MODULE (TIM). Module Objectives. Understand input capture function Understand output compare function Understand pulse width modulation functions Program TIM free running reference clock and options Configure any TIM channel as either: Input capture Output compare PWM.

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TIMER INTERFACE MODULE (TIM)

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  1. TIMER INTERFACE MODULE (TIM)

  2. Module Objectives • Understand input capture function • Understand output compare function • Understand pulse width modulation functions • Program TIM free running reference clock and options • Configure any TIM channel as either: • Input capture • Output compare • PWM TIM Module Exercises Initialize TIM and timer reference counter for 250 ns resolution from 8 MHz system clock Configure channel 1 as input capture Configure channel 2 as output compare Configure channel 3 as buffered 75% duty cycle PWM

  3. IRQ LVI Direct Memory Access Module (DMA) System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) 68HC08 CPU RESET COP BREAK Internal Bus (IBUS) Random Access Memory (RAM) Serial Peripheral Interface (SPI) Electronically Programmable ROM Monitor ROM Serial Communications Interface (SCI) TIMER INTERFACE MODULE • Four programmable channels • Input captures • Rising edge, falling edge, or any edge triggering • Output compares • Set, clear, or toggle actions • Pulse width modulation (PWM) • Buffered or Unbuffered signal generation • Programmable clock input • System clock with prescaler • External TIM Clock input(4 MHz Maximum Frequency) • Free-running or modulo up-count operation • Counter overflow actions • TIM Counter stop and reset • DMA interrupt generation • Modular Architecture Expandable to 8 Channels

  4. PRESCALER TSTOP TRST 16-Bit Counter TOF TOE 16-Bit Comparator TMODH:TMODL 16-Bit Latch Timer Reference Block Diagram PTE3/ TCLK TCLK PRESCALER SELECT Internal BusClock PS2 PS1 PS0 INT Logic D a t a B u s To Channel Logic

  5. Timer Clock Reference • All four timer channels receive their clock reference from • Free running counter • Modulo up counter • Consists of: • 16 bit free running read only timer counter • 16 bit software read/write modulo register • 16 bit comparator (timer counter vs. modulo register) • When counter matches modulo register • Timer Overflow Flag (TOF) set • Counter resets to $0000 • Counter begins counting again • Generated from software selectable clock source • External pin TCLK • Output of 7 bit system clock prescaler

  6. Timer Status and Control Register (TSC) READ: TOF 0 0 TOE TSTOP PS2 PS1 PS0 TSC WRITE: 0 TRST • Timer Status and Control Register (TSC) • Clock select and prescaler bits (PS2-PS0) • Timer Overflow Flag (TOF) Set when 16 bit timer counter resets to $0000 Cleared by reading TSC and then writing logic zero to TOF • If overflow occurs during clearing operation, write has no effect 1 = Timer has reset 0 = Timer has not reset yet • Timer Overflow interrupt Enable (TOE) Enables timer overflow interrupt 1 = Enable interrupt 0 = Disable interrupt RESET: 0 0 1 0 0 0 0 0 • Timer Stop (TSTOP) • Stops the timer counter • Recommended1 = Timer stopped • 0 = Timer active • Timer Reset (TRST) • Resets timer counter AND prescaler • Automatically cleared after counter reset • 1 = Reset counter and prescaler • 0 = No effect • NOTE: Setting both TSTOP and TRST stops the counter $0000

  7. PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal Bus Clock ÷ 1 0 0 1 Internal Bus Clock ÷ 2 0 1 0 Internal Bus Clock ÷ 4 0 1 1 Internal Bus Clock ÷ 8 1 0 0 Internal Bus Clock ÷ 16 1 0 1 Internal Bus Clock ÷ 32 1 1 0 Internal Bus Clock ÷ 64 1 1 1 PTE3/TCLK Timer Prescale Select Bits (PS0-2) NOTE: TCLK pulses must be longer than two system clock pulses or will be ignored

  8. READ: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TCNTH WRITE: RESET: 0 0 0 0 0 0 0 0 READ: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCNTL WRITE: RESET: 0 0 0 0 0 0 0 0 READ: TMODH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 WRITE: RESET: 1 1 1 1 1 1 1 1 READ: TMODL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 WRITE: RESET: 1 1 1 1 1 1 1 1 Timer Counter Register • Timer Counter Register (TCNTH, TCNTL) • 16 bit, read only, free running counter • Reading high byte latches low byte until read Timer Modulo Register • Timer Modulo Register (TMODH, TMODL) • Contents compare against TCNTH, TCHTL to determine reset time • Writing to TMODH disables TOF and overflow interrupts, until write to TMODL

  9. Timer Resolution and Range • Timer resolution is inversely proportional to system clock and prescaler value Resolution (sec) = 1 ÷ (Bus Clock ÷ prescaler) • Timer range depends on value in TMODH and TMODL Range = 0 .. Resolution x TMOD value Max Range = 0 .. Resolution x 65,535 • Example: • Calculate resolution and range given 4 MHz bus clock, prescaler value of 4 (010), and TMOD = $00FF Resolution = 1 ÷ ( 4 MHz ÷ 4 ) = 1 ÷ 1 MHz = 1µs Range = 1µs x $00FF = 1µs x 255 = 255 µs

  10. CHxMAX ELSxB ELSxA TOVx CHxF TCHxH : TCHxL DMASx MSxA Timer Channel Block Diagram From TOF D a t a B u s CHANNEL X PTx Logic PTx/ TCHx 16-bit Comparator X Int Logic 16-bit Latch CHxIE

  11. Input Capture Function • Provides a mechanism to capture the time at which an external event occurs Rising Edges Falling Edges Any Edge TCNTH:TCNTHL Compare/Capture Unit 16-bit Free Running Counter Edge Select & Detect Latch 16-bit Input Capture Latch ICx TCHxH:TCHxL CHxF Status Flag is set upon capture Optional Local Interrupt Mask (enabled through software) Interrupt request to CPU08 CHxIE

  12. T2 T1 Input Capture Example - Measured Pulse Width - 1. Configure timer channel for input capture, rising edge 2. Capture time T1 3. Capture time T2 4. Period = T2 - T1

  13. Output Compare Function • Provides a mechanism to output a signal at a specific time TCNTH:TCNTHL Set Pin Clear Pin Toggle Pin Compare/Capture Unit 16-Bit Free-Running Counter • Possible uses: • Generating waveforms or pulses • Elapsed time indicator (to external circuitry) • Triggering external events Action taken upon match of compare register with counter Pin Control Logic OCx 16-Bit Compare 16-Bit Output Compare Register (programmed by software) Status Flag is set upon compare match CHxF TCHxH:TCHxL Optional Local Interrupt Mask (enabled through software) Interrupt request to CPU08 CHxIE

  14. T2 T1 Output Compare Example- Pulse Generation - • 1. Set compare value to T1 • 2. Configure timer channel for output compare, set output • 3. Set compare value to T2 • 4. Configure timer channel for output compare, clear output • 5. Generated pulse width = T2 - T1

  15. Output Compare Synchronization Method • Interrupt latency and execution time may limit minimum pulse width possible using interrupt on overflow method • To maximize resolution and avoid unsynchronized writes: • Enable the output compare interrupt function when new pulse width value required • Write new value to output compare register within output compare interrupt routine

  16. Timer Overflow Action READ: CHxF TSCx CHxIE MSxB MSxA ELSxB ELSxA TOVx CHxMAX • Timer Channel Status and Control Registers (TSCx) • Toggle on Overflow (TOVx) • Controls behavior Output Compare and PWM only • Has no effect when channel configured as input capture • Normal used in generating PWMs 1 = Toggle Channel output on Timer Overflow 0 = Do nothing on Timer Overflow WRITE: 0 RESET: 0 0 0 0 0 0 0 0 x = Channel number 0, 1, 2, etc.

  17. READ: TCHxH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 WRITE: RESET: INDETERMINATE AFTER RESET READ: TCHxL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 WRITE: RESET: INDETERMINATE AFTER RESET x = Channel number 0, 1, 2, etc. Channel Timer Registers • Timer Channel registers (TCHx) • Input Capture • Timer register value latched upon input capture • Output Compare • Value to compare timer against

  18. Mode MSxB:MSxA ELSxB:ELSxA Configuration • X0 00 Output Preset Pin under port control; initial output lvl high • X1 00 Output Preset Pin under port control; initial output lvl low • 00 01 Input Capture Capture on Rising Edge Only • 00 10 Input Capture Capture on Falling Edge Only • 00 11 Input Capture Capture on ANY (rising or falling) Edge • 01 01 Output Compare Toggle output line on Output Compare • 01 10 Or Clear output line to 0 on output compare • 01 11 PWM Set output line to 1 on output compare • 1X 01 Buffered Output Toggle output on compare • 1X 10 Compare Or Clear output on compare • 1X 10 Buffered PWM Set output on compare Mode, Edge, and Level Selection READ: CHxF TSCx CHxIE MSxB MSxA ELSxB ELSxA TOVx CHxMAX WRITE: 0 RESET: 0 0 0 0 0 0 0 0 x = Channel number 0, 1, 2, etc. Note 1: MSxB has priority over MSxA (When MSxB is set, MSxA is don't care) Note 2: Unbuffered PWMs are set up while in Output Compare Mode

  19. Channel Interrupt & Status READ: CHxF TSCx CHxIE MSxB MSxA ELSxB ELSxA TOVx CHxMAX WRITE: 0 • Timer Channel Status and Control Registers (TSCx) • Channel x Interrupt Enable (CHxE) • Enables TIM CPU interrupts and TIM DMA service requests on channel x. 1 = Channel x CPU interrupt requests and DMA service requests enabled 0 = Channel x CPU interrupt requests and DMA service requests disabled • Channel Status Flag (CHxF) • Input Capture • Set when active edge occurs • Output Compare • Set when the value in TIM counter registers matches value in TIM channel register • Cleared by reading status register then writing logic one to CHxF 1 = Input capture or output compare on channel x 0 = No event capture or output compare on channel x RESET: 0 0 0 0 0 0 0 0 x = Channel number 0, 1, 2, etc.

  20. TIM Exercise • Calculate the register values to configure: • Timer for 8µs resolution from a 4 MHz Bus clock • Timer channel 1 to capture rising edge of a signal • Timer channel 2 to toggle it’s output between states every 100 ms • Given: • MCU has just been reset * Timer exercise TSC EQU $0020 TMODH EQU $0024 TMODL EQU $0025 TSC1 EQU $0029 TSC2 EQU $002C TCH2H EQU $002D TCH2L EQU $002E * Configure Timer for 8µs resolution, using 4 MHz system clock MOV #_30_,TSC ; Reset timer, Configure clock prescaler MOV #_30_,TMODH ;MSB for modulo register MOV #_D4_,TMODL ;LSB for modulo register * Configure Timer channel 1 to capture rising edge of pulse MOV #_04_,TSC1 ;Input capture, rising edge only, no interrupts * Configure Timer channel 2 to toggle output MOV #_30_,TCH2H ;Set compare value MSB MOV #_D4_,TCH2L ;Set compare value LSB MOV #_14_,TSC2 ;Output compare, toggle output, no interrupts BCLR 5,TSC ;Start timer, reset bit automatically clear

  21. Write your program here: DIFF EQU $52 TSC EQU $20 TIME EQU $50 TSC1 EQU $29 TCNTH EQU $22 TCH1L EQU $2B TCH1H EQU $2A TCNTL EQU $23 software polling, non-interrupt-driven, routine. Assume System clock = 8 MHz. Suggested program steps: Measure Period of a Square Wave Exercise Capture function to determine the difference in time from one rising edge to the next. Use a 17. Done, stay here. Write a routine that measures the period of a square wave on TCH1. The routine uses the Input Address of Time (16 bit value) 4. Write a logic "zero" to CH1F. difference between first and next times: Also, first step to clear CH1F flag 8. Store H:X to TIME RAM location. Address of Difference (16 bit value) Clear TIM CH1 flag (CH1F), Start Timer; 12. Subtract TIMEL from accumulator. 11. Load TCH1L count into accumulator. 14. Load TCH1H count into accumulator. 7. Load TCH1H count into H:X Register. 3. Read Timer Channel 1 Status Register. Initialize TIM CH1 for input capture function: 5. Start timer, reset bit automatically clears. Timer Ch. 1 Low Register Timer Ch. 1 High Register 13. Store difference to DIFFL RAM location. 16. Store difference to DIFFH RAM location. 1. Reset Timer and Configure clock Prescaler Timer Counter Register Low Timer Counter Register High 6. Wait here if CH1F flag is not set, else goto 7. Addresses for: Timer Status/Control Register 2. Load TCR with "capture rising edge" value. 10. Wait here if CH1F flag is not set, else goto 11. Configure Timer for 8uS resolution, using 8MHz clock 15. Subtract with borrow TIMEH from accumulator. Get time of next rising edge of square wave & calculate 9. Second step to clear CH1F flag(Write "0" to CH1F) Get time of first rising edge of square wave & clear CH1F: Timer Ch. 1 Status/Control Register HC08-InCapExer

  22. TSC EQU $20 TSC2 EQU $2C TCNTL EQU $23 TCH2L EQU $2E TCNTH EQU $22 TCH2H EQU $2D Write your program here: F (timer clock Frequency) = 4 MHz ÷ 4 = 1 MHz D = Delay from one TCMP clock edge to the next = 500 uSec Total # of timer clocks = F x D = (1 x 10 E6) x (500 x 10 E-6) = 500 7. processor clock = 4 MHz. Use a software polling, non-interrupt driven, routine. 18. Goto step 8. 5. Read TSC2. 1 KHz Square Wave Exercise Write a routine that generates a 1 KHz square wave on the TCH2 pin. Assume the internal Start Timer 11. Save accumulator. 3. Set LSB compare value. 2. Set MSB compare value. 6. Write a logic "0" to CH2F. Clear CH2F flag(2 steps required): Suggested program steps: 15. Get saved delay for TCH2L. 16. Store accumulator to TCH2L. 14. Store accumulator to TCH2H . 10. Add TCH2L value to accumulator. Timer Ch. 2 Low Register Timer Ch. 2 High Register Timer Counter Register Low Timer Counter Register High Addresses for: Timer Status/Control Register 13. Add with carry TCH2H to accumulator. Initialize TIM CH2 to toggle output every 1mS 1. Reset Timer and Configure clock Prescaler Timer Ch. 2 Status/Control Register 12. Load accumulator with hi half of 500 usec delay. Configure Timer for 8uS resolution, using 8MHz clock 17. Write a logic "0" to CH2F, 2nd step to clear flag. 8. Wait for CH2F to go set, also 1st. step to clear flag When CH2F=1 add 500 usec. delay & set for next output: 9. Load Accumulator with low half of 500 usec delay. 4. Load TSC2 with "Toggle output on compare" value. HC08-OutCompExer

  23. Unbuffered PWM Signal • Any channel can generate an unbuffered PWM • Uses output compare • Toggling output based on timer overflow • PWM period set by: • Modulo count value • Clock prescaler output • Pulse width duration set by: • Output compare register value • Timer channel configured to force output pin to complement of pulse width level

  24. T1 T2 TIME B B A A A A = Output compare, clear output occurs B = Timer overflow, toggle output occurs PWM Signal Generation • T1 = PWM Period = Timer overflow point • Calculate prescaler value and TMOD = T1 • T2 = Pulse width = Output compare value • Example: Want 50% duty cycle PWM with period of 100 µs from a 4 MHz system clock. Select prescaler of 4, Resolution = 1 ÷ (4 MHz ÷ 4) = 1µs TMOD = T1 ÷ Resolution = 100µs ÷ 1µs = 100 TCHxH:TCHxL = T2 = Duty cycle x TMOD = 50% x 100 = 50

  25. PWM Resolution • Period • 8-bit PWMs • Variable in 256 increments of system clock • 16-bit PWMs • Variable in 65536 increments of system clock • Pulse width is variable up to N increments of system clock N = System clock counts for Period • Pulse width = N/4 = 25% duty cycle • Pulse width = N/2 = 50% duty cycle • Pulse width = 3N/4 = 75% duty cycle

  26. Unbuffered PWM Initialization • 1) Stop and reset timer • 2) Select timer counter modulo value and timer clock prescaler to provide required PWM period • 3) Load output compare register with pulse width value • 4) Configure timer channel for output compare operation • 5) Select the timer counter toggle on overflow function • 6) Configure timer channel to force output pin to complement of pulse width level • Toggle on output compare should not be used • 7) Enable the timer

  27. 192 Pulse Width Duration= 75% Duty Cycle 256 Frequency ~ 32Khz (8Mhz/256) Unbuffered PWM “Example 1” • Create an eight-bit unbuffered PWM with the following characteristics: • Frequency of approx 32 KHz • Duty cycle of 75% • Initial Pulse Width begins in logic 1 state • Assume: • 8 MHz system clock • Use timer channel 0 • HC08 has just been reset • Steps Required: • Stop and reset timer • Set TSTOP and TRST in TSC register • Configure prescaler and modulo register for 32 KHz • Note PS2:0 in TSC register = 000 (divide by 1) on timer reset • Set TMODH:TMODL = $00FF (8 MHz / 256 ­ 32 KHz) • Configure timer status and control register for channel 0 (TSC0) • Set MS0A = 1 (Output Compare) • Set ELS0B:ELS0A = 10 (Clear output line on output compare) • Set TOV0 = 1 (Enable timer counter toggle on overflow) • Clear CH0E (Disable output compare interrupt) • Load output compare register for pulse width of 192 counts • Set TCH0H = $00, TCH0L = $C0 (192 / 256 = 75%) • Enable the timer • Clear TSTOP in the TSC register

  28. Limitation for Unbuffered PWM • Previous methods for changing pulse widths work in most cases • Except when change in pulse width is large • Example: Could not change from a 99% duty cycle to a 1% duty cycle

  29. From TOF CHxMAX ELSxB ELSxA CHANNEL X PTx Logic PTx/ TCHx TOVx 16-bit Comparator X CHxF TCHxH : TCHxL Int Logic DMASx 16-bit Latch CHxE D a t a B u s MSxA X MSxB CHyMAX ELSyB ELSyA CHANNEL Y PTx Logic PTy/ TCHy TOVy 16-bit Comparator X CHyF TCHyH : TCHyL Int Logic DMASy 16-bit Latch CHyE MSyA Buffered PWMChannel Block Diagram

  30. What is Buffered PWM? • Uses two output compare registers to control a single output • Overcomes synchronization and pulse width limitations of unbuffered PWMs • Channels 0 and 1 and/or channels 2 and 3 may be linked • Selected by setting MS0B and/or MS2B bit • Linked timer channel (ch 1 and/or 3) output becomes general purpose I/O • Under control of DDR and data register • Regardless of TSC1 and/or TSC3 settings HC08 Buffered PWM Operation • Configure either channel 0 or 2 as for unbuffered PWM • Except MSxB bit is set in TSCx register • Initial pulse width must be loaded into channel 0 or 2’s output compare register • Subsequent pulse width values are written to inactive linked channel at any time • Writing to compare register of inactive channel enables that channel • Output control changes after next counter overflow • Auto synchronization

  31. Frequency ~ 32Khz (8Mhz/256) Pulse Width Duration = 254 counts Buffered PWM “ Example 1 “ • Create an eight-bit buffered PWM with following characteristics: • Frequency of approximately • Assume: • System clock is approx 8 Mhz • Use timer channels 0 and 1 • HC08 has just been reset

  32. Frequency = 32Khz Pulse Width = 254 Buffered PWM “ Example 1 Solution “ • Stop and reset the timer • Set TSTOP and TRST in TSC register • Configure prescaler and TMOD register for 32 KHz • Note PS2:0 in TSC register = 000 (divide by 1) on timer reset • Set TMODH:TMODL = $00FF (8 MHz / 256 ­ 32 KHz) • Configure timer status and control register for channel 0 (TSC0) • Set MS0B:MS0A = 11 (Buffered PWM, Output Compare) • Set ELS0B:ELS0A = 10 (Clear output line on output compare) • Set TOV0 = 1 (Enable timer counter toggle on overflow) • Clear CH0E (Disable output compare interrupt) • Load output compare register 0 for pulse width of 254 counts • Set TCH0H = $00, TCH0L = $FE (254 / 256 = 99%) • Enable the timer • Clear TSTOP in TSC register

  33. Pulse Width ModulationBuffered/Unbuffered • Unbuffered PWMs • Advantages • Consistent, non-serviced PWM waveform • Programmable period and duty cycle • Disadvantage • Must synchronize changes to duty cycle • Buffered PWMs • Advantages • Unsynchronized changes to duty cycle, auto sync • Disadvantage • Requires two timer channels • Must keep track of inactive channel

  34. TIM Exercise - Buffered PWM - * Timer exercise - Part 2 TSC EQU $0020 TMODH EQU $0024 TMODL EQU $0025 TSC0 EQU $0026 TCH0H EQU $0027 TCH0L EQU $0028 TSC1 EQU $0029 TCH1H EQU $002A TCH1L EQU $002B * Timer exercise - Part 2 BSET 5,TSC ;Stop timer BSET 4,TSC ;Reset timer * Could pick any period you want, lets choose max in 8-bit PWM, yields ­ 32 KHz MOV #$00,TMODH ;MSB for modulo register MOV #$FF,TMODL ;LSB for modulo register *Want 75% duty cycle = 3/4 * period = 3/4 * 256 = 192 MOV #$00,TCH0H ;Set compare value MSB MOV #$C0,TCH0L ;Set compare value LSB * Configure Timer channel 0 as buffered PWM MOV #$2A,TSC0 ;Buffered PWM, Clear on compare, Enable ;toggle on timer overflow BCLR 5,TSC ;Start timer, reset bit automatically clear • Code configures a Timer channel as a buffered 75% duty cycle PWM. • Assume: • Timer register already configured for 125 ns resolution • TMOD register has not been initialized (default $FFFF) • Pick your own PWM frequency/period • Given:

  35. Additional Timer Questions • a) What is the fastest frequency that can be achieved for a 5-bit PWM? • b) What is the fastest frequency that can be achieved for a 12-bit PWM? • c) What happens when an output compare value is greater than the value in the modulus registers? • d) What happens if the output compare register is the same as the modulus register • e) With ELSxB:ELSxA = 00 (discrete I/O mode), will the timer still generate interrupts if enabled? • f) How do you force an output compare or PWM to begin in a logic zero or logic one state?

  36. Additional Timer QuestionsANSWERS • a) Bus Clock/32 ~ 8Mhz/32 ~ 250 KHz • b) Bus Clock/4096 ~ 8Mhz/4096 ~ 2 KHz • c) The output compare will never occur if the Output Compare register is greater than the modulus register • d) The counter overflow toggle will take precedence (if enabled) over an output compare if they occur at the same time • e) Yes. You must disable the channel interrupts or stop the timer to disable timer interrupts

  37. Additional Timer QuestionsANSWERS • f) To force a channel output to a logic zero: • Set ELSxB:ELSxA = 10 • Ensure (MSxB:)MSxA are set to any state other than (0)0 • Clear the appropriateReset the timer (TRST = 1) • To force a channel output to a logic one: • Set ELSxB:ELSxA = 11 • Ensure (MSxB:)MSxA are set to any state other than (0)0 • Clear the appropriateReset the timer (TRST = 1) • Note: You cannot use I/O port data register and DDR to preset state of an output pin prior to enabling timer channel

  38. READ: CHxF TSCx CHxE MSxB MSxA ELSxB ELSxA TOVx CHxMAX WRITE: 0 RESET: 0 0 0 0 0 0 0 0 x = Channel number 0, 1, 2, etc. 100% Duty Cycle Selection • Timer Channel Status and Control Registers (TSC0 - TSC3) • Channel Max - 100% PWM duty cycle (CHxMAX) • Forces duty cycle to 100% • Takes effect in cycle after being set or cleared 1 = Enable 100 % duty cycle 0 = Disabled

  39. Additional Information- DMA Servicing - READ: 0 0 0 0 TDMA • Timer DMA Select Register (TDMA) • DMA Channel Selects ( DMAS3 - DMAS0) • Selects either CPU or DMA interrupts for that channel 1 = DMA handles channel x interrupts 0 = CPU handles channel x interrupts • NOTE:Channel interrupts are still enabled/disabled by CHxE bit in TSCx register DMA3S DMA2S DMA1S DMA0S WRITE: RESET: 0 0 0 0 0 0 0 0

  40. Additional Information- Low Power Modes - • WAIT • TIM remains active • TIM Registers are not accessible by the CPU • Enabled TIM interrupts can wake processor • DMA can service the TIM without exiting wait mode • If TIM functions are not required during wait mode, stop TIM before executing WAIT instruction • STOP • TIM becomes inactive • Register contents not affected • TIM operation resumes when the MCU exits stop mode after and external interrupt

  41. Register Summary TSC TOF TOIE TSTOP TRST 0 PS2 PS1 PS0 0 0 0 0 DMAS3 DMAS2 DMAS1 DMAS0 TDMA TCNTH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TCNTL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TMODH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TMODL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TCS0 CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MX TCH0H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TCH0L BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 • • • • • • TCSn CHnF CHnIE 0 MSnA ELSnB ELSnA TOVn CHnMX TCHnH BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 TCHnL BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

  42. STA DIFF SBC TIME LDA TSC1 DIFF EQU $52 STHX TIME TSC EQU $20 TIME EQU $50 STA DIFF+1 LDA TCH1L BCLR #5,TSC TSC1 EQU $29 LDA TCH1H SUB TIME+1 LDHX TCH1H TCH1L EQU $2B BCLR #7,TSC1 TCNTH EQU $22 BCLR #7,TSC1 TCH1H EQU $2A DONE BRA DONE TCNTL EQU $23 MOV #$04,TSC1 MOV #$36,TSC Write your program here: WAIT1 BRCLR #7,TSC1,WAIT1 WAIT2 BRCLR #7,TSC1,WAIT2 software polling, non-interrupt-driven, routine. Assume System clock = 8 MHz. Measure Period of a Square Wave Solution Capture function to determine the difference in time from one rising edge to the next. Use a 17. Done, stay here. Write a routine that measures the period of a square wave on TCH1. The routine uses the Input Address of Time (16 bit value) 4. Write a logic "zero" to CH1F. difference between first and next times: Suggested program steps: Also, first step to clear CH1F flag 8. Store H:X to TIME RAM location. Address of Difference (16 bit value) Clear TIM CH1 flag (CH1F), Start Timer; 12. Subtract TIMEL from accumulator. 11. Load TCH1L count into accumulator. 14. Load TCH1H count into accumulator. 7. Load TCH1H count into H:X Register. 3. Read Timer Channel 1 Status Register. Initialize TIM CH1 for input capture function: Timer Ch. 1 Low Register 5. Start timer, reset bit automatically clears. Timer Ch. 1 High Register 13. Store difference to DIFFL RAM location. 16. Store difference to DIFFH RAM location. 1. Reset Timer and Configure clock Prescaler Timer Counter Register Low Timer Counter Register High 6. Wait here if CH1F flag is not set, else goto 7. Addresses for: Timer Status/Control Register 2. Load TCR with "capture rising edge" value. 10. Wait here if CH1F flag is not set, else goto 11. Configure Timer for 8uS resolution, using 8MHz clock 15. Subtract with borrow TIMEH from accumulator. Get time of next rising edge of square wave & calculate 9. Second step to clear CH1F flag(Write "0" to CH1F) Get time of first rising edge of square wave & clear CH1F: Timer Ch. 1 Status/Control Register HC08-InCapSol

  43. TAX LDA #1 LDA #$F4 BRA WAIT TSC EQU $20 TSC2 EQU $2C STX TCH2L STA TCH2H TCNTL EQU $23 ADD TCH2L ADC TCH2H TCH2L EQU $2E TCNTH EQU $22 TCH2H EQU $2D BCLR #5,TSC BCLR #7,TSC2 BCLR #7,TSC2 MOV #$36,TSC MOV #$14,TSC2 MOV #$01,TCH2L MOV #$F4,TCH2H Write your program here: WAIT BRCLR #7,TSC2,WAIT F (timer clock Frequency) = 4 MHz ÷ 4 = 1 MHz D = Delay from one TCMP clock edge to the next = 500 uSec Total # of timer clocks = F x D = (1 x 10 E6) x (500 x 10 E-6) = 500 7. processor clock = 4 MHz. Use a software polling, non-interrupt driven, routine. 18. Goto step 8. 5. Read TSC2. 1 KHz Square Wave Exercise Write a routine that generates a 1 KHz square wave on the TCH2 pin. Assume the internal Start Timer 11. Save accumulator. 3. Set LSB compare value. 2. Set MSB compare value. 6. Write a logic "0" to CH2F. Clear CH2F flag(2 steps required): Suggested program steps: 15. Get saved delay for TCH2L. 16. Store accumulator to TCH2L. 14. Store accumulator to TCH2H . 10. Add TCH2L value to accumulator. Timer Ch. 2 Low Register Timer Ch. 2 High Register Timer Counter Register Low Timer Counter Register High Addresses for: Timer Status/Control Register 13. Add with carry TCH2H to accumulator. Initialize TIM CH2 to toggle output every 1mS 1. Reset Timer and Configure clock Prescaler Timer Ch. 2 Status/Control Register 12. Load accumulator with hi half of 500 usec delay. Configure Timer for 8uS resolution, using 8MHz clock 17. Write a logic "0" to CH2F, 2nd step to clear flag. 8. Wait for CH2F to go set, also 1st. step to clear flag When CH2F=1 add 500 usec. delay & set for next output: 9. Load Accumulator with low half of 500 usec delay. 4. Load TSC2 with "Toggle output on compare" value. HC08-OutCompSol

  44. Timer Block Diagram TCLK PTE3/TCLK PRESCALER SELECT INTERNAL PRESCALER BUS CLOCK TSTOP PS2 PS1 PS0 TRST 16-BIT COUNTER INTER- TOF RUPT LOGIC TOIE 16-BIT COMPARATOR TMODH:TMODL TOV0 ELS0B ELS0A PTE4 CHANNEL 0 CH0MAX PTE4/TCH0 LOGIC 16-BIT COMPARATOR TCH0H:TCH0L CH0F INTER- 16-BIT LATCH DMA0S RUPT LOGIC MS0A CH0IE MS0B INTERNAL BUS TOV1 ELS1B ELS1A PTE5 CHANNEL 1 CH1MAX PTE5/TCH1 LOGIC 16-BIT COMPARATOR TCH1H:TCH1L CH1F INTER- 16-BIT LATCH DMA1S RUPT LOGIC MS1A CH1IE TOV2 ELS2B ELS2A PTE6 CHANNEL 2 CH2MAX PTE6/TCH2 LOGIC 16-BIT COMPARATOR TCH2H:TCH2L CH2F INTER- 16-BIT LATCH DMA2S RUPT LOGIC MS2A CH2IE MS2B TOV3 ELS3B ELS3A PTE7 CHANNEL 3 CH3MAX PTE7/TCH3 LOGIC 16-BIT COMPARATOR TCH3H:TCH3L CH3F INTER- 16-BIT LATCH DMA3S RUPT LOGIC MS3A CH3IE TIM V2.1 9 - 12

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