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CAVA: Open Source Infrastructure for System-On-a-Chip Designs

CAVA: Open Source Infrastructure for System-On-a-Chip Designs. Peter Hsu, Ph.D. Peter Hsu Consulting, Inc. 43551 Mission Blvd., Fremont, CA 94539 email: peterhsu@cs.wisc.edu Presented 14 March 2002 at the University of Wisconsin in Madison. Design Infrastructure.

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CAVA: Open Source Infrastructure for System-On-a-Chip Designs

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  1. CAVA: Open Source Infrastructure for System-On-a-Chip Designs Peter Hsu, Ph.D. Peter Hsu Consulting, Inc. 43551 Mission Blvd., Fremont, CA 94539 email: peterhsu@cs.wisc.edu Presented 14 March 2002 at the University of Wisconsin in Madison

  2. Design Infrastructure • Hardware “Intellectual Properties” • Processor Core(s) • Multiprocessor Bus, External Interfaces • Software Development Environment • Gnu Compiler gcc, as, ld; Utilities glibc, gdb, … • Linux Operating System Kernel, Drivers • Analysis Tools • Performance Simulator(s) • Architecture Verification Programs CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  3. CPU L1$ I/O interface I/O interface I/O interface CPU CPU CPU L1$ L1$ L1$ I/O interface CPU L1$ Application Specific Logic New Insns Complex I/O interface Multiprocessor Organization Memory Controller CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  4. Cost-Performance Evolution 1 GHz 15 0.09µm 90% yield $2 0.13µm 1000 / wafer 85% yield $4 2-4 CPUs 8MB DRAM $5 30 800 MHz 30 ? 0.18µm 500 / wafer 70% yield $10 600 MHz +30% ? 60mm2 400 MHz CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  5. Author’s Perspective • Maybe Boring… • “Decent Computer Using Crummy Technology” • Example: Seymore Cray’s vs. IBM’s Approach • “Get More out of Existing Technology” • Hybrid Petro/Electric Car • Cost Drives Application Breadth • “900 Mips Make A Better Light Bulb” • “Earing PDA Helps You Remember Dates” • “Silicon Sequin Dress Adapts to Weather” CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  6. Efficiency Matters: F ·C · V2 • Frequency (F) • Fewer Instructions, Lower Latencies • Capacitance (C) • Fewer Gates, Narrower Bus, … • Voltage (V) • Slower Gates, Less Logic per Cycle • Same Design: • 600 MHz, 1.2 V, 4W½W, 250 MHz, 0.6 V CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  7. Why Open Source? • Embedded Market • High Volume  Low Prices  Little Profit  Small Engineering Budget  Few Inventions… • Most SoC Use 1970’s Architecture • Motorola 6800, x86 Family, e.g. z80 • Royalty Payment Based Innovation • ARM, MIPS, Tensilica, … Future Unclear • Industry Ripe for New Market Dynamics • Cava Set New Cost-Performance Standard? • No Royalties New Players  Opportunities CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  8. Key Decisions • “RTL” Design • Integration Effort, Process Migration, Accessibility • More Important Than Pure Performance Logic Synthesis, Standard Cells, P&R • No Dynamic Circuits, No Custom Layout • New ISA • Companies: “Open” Architectures Feel “Unsafe” • Originator Company Big and Mean? • Neutrality: “Perception is Reality” • Ex: Linux Very x86-centric, but Perceived Otherwise CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  9. Why ASIC CPU Usually Slow? • Design Issue • C-MOS vs. Dynamic Circuits • High Fan-In Gate: Cache Hit Detection, TLB • ASIC SRAM Very Fast (“Hard Macro”) • Fruitful Area for Innovations… • Manufacturing Issue • Make Few Wafers  Worse-Case Design • Make Many Wafers  Typically 50% Faster • 2GHz Pentium 4, ISSCC Chips • SoC: “Make Cheaper, Goes Faster” CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  10. Adder Tag Tag Data Data =? =? Ex: Tag Match Critical Path • Dynamic vs. Static • Adder 20 30 • Tag 15 25 • Data 20 25 • Match 5 20 • 2-Cycle Load • D: (20+15+5)2 = 20 • S: (30+25+20)2 = 38 • 800 vs. 400 MHz • Inv. Delay = 63ps 30 25 20 CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  11. =? Adder Adder Tag Recurrance Forward Substitution • Replicate ALU • (30+25)2 = 27.5 • 600 MHz • vs. 800, 400 MHz • 5K gates  0.1mm2 • Opportunity? • Most CPU Knowledge from Custom Designs • Experiment Using Logic Synthesis, Place&Route 20 30 =? 25 25 Tag Data Data CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  12. op 8 op disp imm y y op 6 y x 6 x x x - - - op 4 32-bit address op x - 24-bit offset Instruction Set • RISC Lessons Many Registers Everything Else? • Code Density • Silicon: CPU  3 MBytes of DRAM • Applications: Millions of Lines of Code • 24-bit Instructions • Two 64-reg Specifiers x = x op y x = x op imm x = *(y+disp) CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  13. Variable Length Instructions • Superscalar Paradigm • Speculatively Decode, Ignore Some • Middle vs. Always Instructions At End • Idiom Acceleration • Set high 16bit + load with 16bit displacement • Key Features • Lengths In Multiples (Semour Cray’s Parcel) • Else Many Wasted Decode Stations • Opcode, Register Fields in 1st Parcel • Single-Issue Design Conserve Gates, Power CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  14. Mem Ctrl Superscalar Uniprocessor Eth1 USB PCI 1 Mem Ctrl CPU + Thin I/O Eth2 PCI 2 CPU + Thin I/O CPU + Thin I/O Why Multiprocessor Architecture? • Efficiency • Area • More Mips per Gate • Power • Less Synchronous • Effective Clock Gating • Ease of Use • Real Time • vs. Fancy Scheduling • Customization Conventional Integration CAVA-1 CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  15. I/O Architecture Evolution • Typical I/O Controller Chip • Mixed Analog/Digital Physical Media Interface • Protocol Encapsulation, Error Handling • Flow Control, Interrupts, DMA, Buffering • Market Forces • Complex Controller Chips are Cost Effective • Economy of Scale Outweights Gate Utilization • Integrate Existing Chips into SoC • Minimize Engineering, Less “Risk” • Is “Holistic” Solution Better? CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  16. CAVA I/O Architecture • Processor Doubles As I/O Controller • “Background” Context • 64 Registers, Overlapped Execution, Speculative • “Foreground” Context • 4 Registers, De-pipelined ( 1 Instruction / 4 Clocks) • Branch on I/O Register Bit (e.g. Error, Data Ready…) • Dedicated Gates: Only Physical Media Interface • Open Questions • Efficiency? Dedicated Logic? Interference? • Need Good Abstraction CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  17. CAVA-1 Memory System • Initial Target • No L2 Cache • If 6-T Memory Cell  Bigger L1,  Same Cycle Time • Not Rambus • Royalty Payment, RAC Process Migration Difficulties • DRAM • FCRAM: “Slightly Better DRAM” • Cache Miss Penalty  50ns = 30 Cycles @ 600 MHz • 64-bit Interface  2.4GB/s  1 Byte/Cycle/CPU • Flexibility Very Important • Also Use Standard DDR SDRAM • 64-, 32- and 16-bit wide (4, 2 or 1 chips) CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  18. Multi-Thread Support • Memory Latency Impact • 5% miss  30 cycles = 1.5 cpi  Half Idle • Significant Improvement: Lots of Silicon Area • 2-Port SRAM as Register File • 64  64 256  64: +50% Area • CAVA-1: 3 Background, 16 Foreground • Interesting Questions • “Helper Thread” for Serial Program? • Quantify Speculation Area, Clock Speed, Perf. CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  19. Project Status/Roadmap • Phase 1: Running (Limping ;-) • gcc, as, ld, glibc, gdb, ISA emulator • Phase 2: Fall 2002 • Linux Kernel, I/O Controller Programs • Standalone PC Emulator, FPGA PCI Card for I/O? • Key Decisions re: Verification Strategy • Quantitative Analysis of Clock Cycle • Target 600 MHz 0.18µm(typ. process, w.c. env.) • Phase 3: Spring 2003 • Design RTL, Tapeout, Party, Debug, … CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  20. ISA Research Tool • Instruction Descriptions • Syntax.in • Lengths, Field Definitions, Opcode Encodings iR imm[8] [6] x[6] [4=0] # Immediate with Register bR [8] y[6] x[6] [4=F] # Binary Register Operator • Semantics.in • Gcc “.md” Patterns, Emulator C Statement iR,ia addi x += imm # Add Immediate (set (match_operand:DI “register_operand” “=r”) (plus:DI (match_operand:DI “register_operand” “%0”) (match_operand:DI “immediate_operand” “I”)) • Consistent gcc, as, ld, gdb, emulator, doc CAVA: Open Source Infrastructure for System-On-a-Chip Designs

  21. Conclusion • New Technology • Creation: Only Beginning • Adoption: Critical Mass, Understand, Can Modify • Necessary to Evangelize, to Share • Vision • Modular Architectural Enhancements by Many • Invent Novel SoC’s, Uninhibited by Lawyers • It’s Fun! • Periodic Open Releases of Compiler, RTL • Participate: Build Computer System from Scratch CAVA: Open Source Infrastructure for System-On-a-Chip Designs

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