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Assembly and Packaging

Assembly and Packaging. Assembly and Packaging Technical Working Group – 2012 (83 Participants). Sai Ankireddi, Souvik Banarjee , Bernd Appelt, Thomas Baer, Muhannad S. Bakir,

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Assembly and Packaging

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  1. Assembly and Packaging

  2. Assembly and Packaging Technical Working Group – 2012 (83 Participants) Sai Ankireddi, Souvik Banarjee, Bernd Appelt, Thomas Baer, Muhannad S. Bakir, Hans-Joachim Barth, Steve Bezuk, W.R. Bottoms, William Burdick, Yi-jen Chan, Carl Chen, William Chen, Sonjin Cho, Yulkyo Chung, Bob Chylak, Horst Clauberg, Mark De Samber, Krishor Desai, Dan Evans, Bradford Factor, Tatsuhiro Fujiki, Michel Garnier, Steve Greathouse, Tom Gregorich, Richard Grzybowski, George Harman, Tomoo Hayashi, Willem Hoving, Mike Hung, John Hunt, T. S. Hwang, Kazuyuki Imamura, Dan Kilper, Mitchitaka Kimura, Shoji Kitamura, Tzu-Kun Ku, Choon Heung Lee, Ricky S W Lee, Rong-Shen Lee, Russell Lewis, Sebastian Liau, Weichung Lo, Debendra Mallik, Kaneto Matsushita, Stan Mihelcic, David Miller, Hirofumi Nakajima, Keith Newman, Gary Nicholls, Grace Omalley, John Osenbach, Richard F. Otte, Bob Pfahl, Gilles Poupon, Klaus Pressel, Gamal Refai-Ahmed, Charles Reynolds, Charles Richardson, Philippe Robert, Peter Robinson, Bernd Roemer, Gurtej Sandu, Robert Sankman, Naoto Sasaki, Shahriar Shahramian, Vern Solberg, KaoruSonobe, Simon Stacey, Yoshiaki Sugizaki, Teresa Sze, Coen Tak, Patrick Thompson, Andy Tseng, Shigeyuki Ueda, Henry Utsunomiya, Kripesh Vaidyanathan, Freek Van Straten, Patrick Thompson, Julien Vittu, James Wilcox, Max Juergen Wolf, Jie Xue, Hiroyoshi Yoshida.

  3. Assembly and Packaging Technical Working Group - 2012 • 83 Members Participated in 2012 • Focus of activities for 2012 • Modification of Tables • Preparing for Expanded coverage in 2013: • Expanded coverage for 2.5D, 3D and interposers • Expanded coverage of packaging for photonics • Handling of thinned wafers and die • New materials • MEMS Packaging • Prepare for new coverage of packaging for power devices • Cross TWG coordination • Collaborations include Design, ERM, ERD, ESH, Interconnect, MEMS, Test • Coordination with other Roadmaps • iNEMI • CTR/MPC • JISSO • Greentouch Consortia

  4. Innovation in Single Chip Packaging Continues Despite the rapid growth in the multi-chip package architectures, single chip packages still account for a majority of the electronic products shipped. Innovation in single chip packaging continues at a fast pace to lower cost, decrease size, increase performance and accommodate new circuit types. • Copper Wire bonds (requires new molding compounds) • Copper pillar: (requires new UBM structure, underfill materials) • Tablets and smart phones: QFN and other thin packaging • Network and data center: Ultra-low alpha, large die flip chip • Photonics components (requires optical connection) • MEMS packaging (may require open package and are stress sensitive)

  5. Portable Consumer Products are the Market Drivers The dramatic rise of the mobile device market with smart phones, tablets, portable personal devices, and portable entertainment systems has expanded packaging challenges in: • Form factor (height and area), • weight, • Functional diversification such as RF and video, • System integration, • Reliability, • Power requirement, • Time to market, • Cost.

  6. These Market Forces demand Packaging Innovation • New Processes • Wafer level packaging • Reconstituted wafers • 2.5D and 3D integration • Wafer thinning (and handling thinned wafers during packaging) • New co-design and Simulation tools • New Materials • Dielectrics • Conductors • Barrier layers • Adhesives • Nano-materials

  7. New Device and Package Types are entering the Roadmap • Power devices (including SiC and GaN semiconductors) • MEMS packaging(limited coverage in Prior years will expand in 2013) • 3D Wafer Level Packages • Complex 3D-TSV based System in Package • Photonics to the Package

  8. Industry Challenges Drive Packaging Innovation The landscape for data processing and data communication has changed dramatically in recent years with “all data everywhere all the time” driving explosive growth in communications bandwidth. The cumulative average annual growth rate (CAAGR) is forecast to continue above 100% at least through 2015. This drives critical challenges for the electronics industry including: • Increasing bandwidth density at every point in the data communications infrastructure • (Including physical density of bandwidth in packages) • Decreasing power per unit function in data centers and communications infrastructure • Target is more than 2 orders of magnitude in by 2022

  9. These Goals cannot be met without new Capability for Design and Simulation Co-design and simulation for Chip-Package-System are essential Cost and time to market demands that experiments move from physical prototypes to the computer

  10. Innovation in Wafer level Packaging Development of WLP and FOWLP technology will provide an expanded list of options for Consumer applications. • Thin WLCSP for mobile products • Large WLCSP for reduced cost and increased performance • WLCSP for Power devices • Incorporation of new embedded components • Incorporation of include multi-die (side by side and stacking) These innovations provide a path to further reductions in cost, size and power while increasing performance.

  11. Innovation in Fan-Out Wafer Level Packaging • Small Die/Package • 2.2 x 2.2 mm² • Large Package • 13 x 13 mm² w/ 3 dies • First FOWLP • Mass production : • 8 x 8 mm² • 2D Multi-die • 8.5 x 4.5 mm² w/ 2 dies Source: ASE Group

  12. Coverage of Emerging Requirements for 2013:Interposers 2.5D interposers are in production and coming down the learning curve to reduce cost. Future interposers for 3D integration may incorporate: • Built in self test (BIST) engines, • Switch matrices, • Passive networks, • Microfluidic cooling. These interposers will enable full 3D integration providing for heterogeneous die stacking, test solutions, thermal management and decoupling capacitors to ensure power integrity in stacked die.

  13. Complex SiP have many Challenges System in Package must deal with all the challenges of single chip packages in addition to new challenges such as: • Differential thermal expansion associated with heterogeneous integration • Hot spots • Integration of MEMS, RF, photonics, power and CMOS components into a single package • Isolation of components within the package to limit cross-talk and other noise sources • Power integrity for multiple voltages in the package

  14. System in Package use is Expanding (Comparison with traditional packaging is compelling)

  15. Assembly and Packaging Difficult Challenges

  16. Assembly and Packaging Difficult Challenges

  17. Assembly and Packaging Difficult Challenges

  18. Conclusions Packaging is both enabler and limiter in cost, performance and time to market for consumer products. The pace of innovation in packaging is at an all time high to enable complex 3D SiP products and decrease the scaling gap between semiconductor fabrication and packaging.

  19. Thank You

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