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Optimizations for Faster Execution of Esterel Programs

Optimizations for Faster Execution of Esterel Programs. Dumitru Potop Robert de Simone IRISA Rennes INRIA Sophia Antipolis. Outline. The Esterel language The problem of efficient code generation The GRC intermediate representation Intuitive description

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Optimizations for Faster Execution of Esterel Programs

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  1. Optimizations for Faster Execution of Esterel Programs Dumitru Potop Robert de Simone IRISA Rennes INRIA Sophia Antipolis

  2. Outline • The Esterel language • The problem of efficient code generation • The GRC intermediate representation • Intuitive description • Software code generation • Code analysis and optimizations • Practical results. Conclusion. Future work

  3. The Esterel language • Formal semantics (FSMs, circuits) • Formal verification Esterel specification SW translation HW (RTL) generation • Simulation • SW implementation • HW prototype (FPGA) • Synthesis input

  4. The Esterel language • Reactive, clock-driven execution module ABRO: input A,B,R; output O; » loop [ await A || await B ]; emit O; halt every R end module

  5. The Esterel language • Reactive, clock-driven execution module ABRO: input A,B,R; output O; loop [ await A || await B ]; emit O; halt every R end module

  6. The Esterel language • Reactive, clock-driven execution module ABRO: input A,B,R; output O; loop [ await A || await B ]; emit O; halt every R end module

  7. The Esterel language • Reactive, clock-driven execution module ABRO: input A,B,R; output O; loop [ await A || await B ]; emit O; halt every R end module

  8. The Esterel language • Synchrony • Causality cycles present S else emit S end • Constructive semantics (SOS rules) ·signal S,T in emit S; present T then present S else emit T end else emit O end; end

  9. The Esterel language • Synchrony • Causality cycles present S else emit S end • Constructive semantics (SOS rules) signal S,T in ·emit S; present T then present S else emit T end else emit O end; end

  10. The Esterel language • Synchrony • Causality cycles present S else emit S end • Constructive semantics (SOS rules) signal S,T in emit S; ·present T then present S else emit T end else emit O end; end

  11. The Esterel language • Synchrony • Causality cycles present S else emit S end • Constructive semantics (SOS rules) causality cycle signal S,T in emit S; ·present T then present S else emit T end else emit O end; end

  12. The Esterel language • Synchrony • Causality cycles present S else emit S end • Constructive semantics (SOS rules) causality cycle signal S,T in emit S; ·present T then present S else emit T end else emit O end; end break the cycle

  13. First compilation scheme (1980’s) • FSM-based translation • Exhaustive semantic expansion • Explosion in size, expensive analysis • Fast code (execute only active code) 0 loop [ await A || await B ]; emit O; halt every R 1 2 3 4

  14. Second compilation scheme (1990’s) • Circuit-based translation • Encode primitives into gates • Small circuit size (quasi-linear) • Slow software code (acyclic circuit evaluation) A loop [ await A || await B ]; emit O; halt every R R O start B

  15. Third compilation scheme (2000’s) • “Simulation” code • Follows the naïve semantics (control-flow) • Accept less programs (acyclic circuits) • Code:small andvery fast(statically scheduled) • Edwards, Closse/Weil if(START){A_active=1;B_active=1;START=0} else { if(R){A_active=1;B_active=1;} else if(A_active|B_active) { if(A_active) if(A) A_active=0; if(B_active) if(B) B_active=0; if(!(A_active|B_active)) O=1; } } loop [ await A || await B ]; emit O; halt every R

  16. Third compilation scheme (2000’s) • My goal:Formal intermediate model • Preserve high-level information from Esterel (Static analysis, optimization techniques) • Relation with constructive semantics (soundness of analysis and optimization) • Relation with the circuit translation (soundness of execution, unique notion of acyclicity)

  17. The GRC intermediate format 1 boot: 0 # Hierarchical state (structure) 4 await A 3 || await B 2 5 loop [ await A;emit B || await B ]; emit O; halt every R # sequence loop-every halt 6 activation new state enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A Control/Data flow graph (behaviour) [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] B 3 pause[5]

  18. The hierarchical state structure 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 • parallel/exclusive abstraction of the syntax tree • nodes represent the activity condition of various subprogram fragments

  19. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] B 3 pause[5]

  20. Activated from the hierarchical state Flowgraph execution 1 boot: • loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  21. Activated from the hierarchical state Flowgraph execution 1 boot: •loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O • term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  22. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B •|| await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] • Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  23. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ •await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] • pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  24. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;•emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  25. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B• || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  26. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B || await B ]; •emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  27. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B || await B ]; emit O; •halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  28. Activated from the hierarchical state Flowgraph execution 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # sequence loop-every halt 6 enter4 exit 1 enter2 enter3 3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B term[4] exit3 enter6 emit O term A [3] pause 3 pause[4] Inactive[5] 2 [6] 5 exit5 term[5] Rabsent, Apresent B 3 pause[5]

  29. Simulation code generation • State encoding • Static scheduling • Sequential code • Respects the causality (signal emission statements before tests statements)

  30. Simulation code generation boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 S[3]=1 S[1]=1 S[2]=0 3 S[4]=1 S[1] Inactive[4] S[3] R S[3]=0 emit B term[4] term S[2]=1 emit O A pause 3 pause[4] Inactive[5] S[4] S[2] S[4]=0 term[5] B 3 pause[5]

  31. Simulation code generation bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} if(S[4])if(B)S[4]=0; if(S[3]=0&S[4]=0){ O=1;S[2]=1; } }} } else {aux=1;} if(aux){S[1..4]=1011;} • Static scheduling S[1..4]=1011 S[1] Inactive[4] S[3] R S[3]=0 emit B term[4] S[2]=1 term emit O A pause 3 pause[4] Inactive[5] S[4] S[2] S[4]=0 term[5] B 3 pause[5]

  32. Optimizations • Based on static analysis (semantic-preserving, fast, efficient) • Redundant state bit elimination • False signal/data dependency elimination • Node grouping • Dead code removal

  33. Optimizations • Utility • Simplify the state access/update protocol • Simplify the state encoding boot: • Static analysis, example trap T in sustain A || await B;await C;exit T end # nt: sustain A || await B Same status at all instants # nt: await C

  34. GRC code optimizations 1 boot: 0 3 # • Dependency removal pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

  35. GRC code optimizations 1 boot: 0 3 # • Dependency removal pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

  36. GRC code optimizations 1 boot: 0 3 # • Dependency removal pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

  37. Results • Optimizing compiler • Examples: • Turbo channel bus • Berry’s wristwatch • Video generator • Shock absorber • Operating system model • Avionics fuel controller • Avionics cockpit • Man-machine interface Test configuration: PIII/1GHz/128M/Linux gcc-2.96 –O, 1Mcycle random or given

  38. Conclusion • Intermediate model for Esterel programs • Static analysis, optimizations at GRC level • GRC-acyclic = circuit-acyclic • Code generation scheme • Good practical results

  39. Future work • Digital circuit synthesis • State encoding + translation into gates • Good partial results • Distributed implementation • Connection between Esterel and Signal at source or GRC/HCDG level Control registers Control clock hierarchy

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