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Lecture 23 Virtual Memory (2)

CS 15-447: Computer Architecture. Lecture 23 Virtual Memory (2). November 21, 2007 Karem A. Sakallah. Last Lecture. Virtual memory lets the programmer “see” a memory array larger than the DRAM available on a particular computer system.

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Lecture 23 Virtual Memory (2)

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  1. CS 15-447: Computer Architecture Lecture 23Virtual Memory (2) November 21, 2007 Karem A. Sakallah

  2. Last Lecture • Virtual memory lets the programmer “see” a memory array larger than the DRAM available on a particular computer system. • Virtual memory enables multiple programs to share the physical memory without: • Knowing other programs exist (transparency). • Worrying about one program modifying the data contents of another (protection).

  3. Other VM Functions • Page data location • Physical memory, disk, uninitialized data • Access permissions • Read only pages for instructions • Gathering access information • Identifying dirty pages by tracking stores • Identifying accesses to help determine LRU candidate

  4. Page Replacement Strategies • Page table indirection enables a fully associative mapping between virtual and physical pages. • How do we implement LRU? • True LRU is expensive, but LRU is a heuristic anyway, so approximating LRU is fine • Reference bit on page, cleared occasionally by operating system. Then pick any “unreferenced” page to evict.

  5. Performance of Virtual Memory • We must access physical memory to access the page table to make the translation from a virtual address to a physical one • Then we access physical memory again to get (or store) the data • A load instruction performs at least 2 memory reads • A store instruction performs at least 1 read and then a write.

  6. Translation Lookaside Buffer • We fix this performance problem by avoiding memory in the translation from virtual to physical pages. • We buffer the common translations in a translation lookaside buffer (TLB)

  7. TLB Virtual page Pg offset v tag Physical page

  8. Where is the TLB Lookup? • We put the TLB lookup in the pipeline after the virtual address is calculated and before the memory reference is performed. • This may be before or during the data cache access. • Without a TLB we need to perform the translation during the memory stage of the pipeline.

  9. Placing Caches in a VM System • VM systems give us two different addresses: virtual and physical • Which address should we use to access the data cache? • Virtual address (before VM translation) • Faster access? More complex? • Physical address (after VM translations) • Delayed access?

  10. Physically-Addressed Caches • Perform TLB lookup before cache tag comparison. • Use bits from physical address to index set • Use bits from physical address to compare tag • Slower access? • Tag lookup takes place after the TLB lookup. • Simplifies some VM management • When switching processes, TLB must be invalidated, but cache OK to stay as is.

  11. Picture of Physical Caches Virtual address Virtual page Page offset tag PPN tag PPN tag PPN Cache Tag cmp tag PPN Set0 tag Set0 tag PPN Page offset Set1 tag Block offset Set1 tag Tag cmp index tag Set2 tag Set2 tag

  12. Virtually-Addressed Caches • Perform the TLB lookup at the same time as the cache tag compare. • Uses bits from the virtual address to index the cache set • Uses bits from the virtual address for tag match. • Problems: • Aliasing: Two processes may refer to the same physical location with different virtual addresses. • When switching processes, TLB must be invalidated, and dirty cache blocks must be written back to memory.

  13. Picture of Virtual Caches Virtual address tag index Block offset Tag cmp Set0 tag Set0 tag Set1 tag Set1 tag Tag cmp Set2 tag Set2 tag • TLB is accessed in parallel with cache lookup • Physical address is used to access main memory in case of a cache miss.

  14. OS Support for Virtual Memory • It must be able to modify the page table register, update page table values, etc. • To enable the OS to do this, AND not the user program, we have different execution modes for a process – one which has executive (or supervisor or kernel level) permissions and one that has user level permissions.

  15. Extended Example: Loading a Program into Memory Memory Disk Pages 2 entry TLB 0 1 2 3 Page Table Physical Refs 0 References 0000 0004 7FFC 0008 2134 1 2 1000 text1 3 1001 text2 4 1002 Istatic 5 1003 6 7

  16. Additional Information • Page size = 4KB • Page table entry size = 4B • Page table register points to physical address 0000

  17. Step 1: Read Executable Headerand Initialize Page Table Memory Disk Pages 2 entry TLB 0 reserved 1 2 3 Page Table Physical Refs 0 D1000 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  18. Step 2: Load PC from Headerand Start Execution Memory Disk Pages 2 entry TLB MISS! 0 reserved 1 2 3 Page Table Physical Refs 0 D1000 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  19. Fetching instr 0000 Memory Disk Pages 2 entry TLB 0 reserved 1 2 3 Page Table Physical Refs 0000 Page fault 0 D1000 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  20. Fetching instr 0000 Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 2 3 Page Table Physical Refs 0000 Page fault 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  21. Fetching instr 0000 Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 2 3 Page Table Physical Refs 0000 Page fault 1000 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  22. Fetching instr 0004 Memory Disk Pages 2 entry TLB HIT! 0 reserved 0000 M1 ro 1 text1 2 3 Page Table Physical Refs 0000 Page fault 1000 1004 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  23. Reference 7FFC Memory Disk Pages 2 entry TLB MISS! 0 reserved 0000 M1 ro 1 text1 2 3 Page Table Physical Refs 0000 Page fault 1000 1004 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  24. Reference 7FFC Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 2 3 Page Table Physical Refs 0000 Page fault 1000 1004 No map page fault 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 no map

  25. Reference 7FFC Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 7000 M2 rw 2 Set to 0s 3 Page Table Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 M2

  26. Fetching instr 0008 Memory Disk Pages 2 entry TLB HIT! 0 reserved 0000 M1 ro 1 text1 7000 M2 rw 2 Set to 0s 3 Page Table Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 M2

  27. Reference 2134 Memory Disk Pages 2 entry TLB MISS! 0 reserved 0000 M1 ro 1 text1 7000 M2 rw 2 Set to 0s 3 Page Table Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 M2

  28. Reference 2134 Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 7000 M2 rw 2 Set to 0s 3 Page Table Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 Page fault 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 D1002 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 M2

  29. Reference 2134 Memory Disk Pages 2 entry TLB 0 reserved 0000 M1 ro 1 text1 2000 M3 rw 2 Set to 0s 3 Page Table Istatic Physical Refs 0000 Page fault 1000 1004 No map page fault 2FFC 1008 Page fault 3134 0 M1 ro References 0000 0004 7FFC 0008 2134 ro 1 D1001 2 M3 1000 text1 3 no map 1001 text2 4 no map 1002 Istatic 5 no map 1003 6 no map 7 M2

  30. Multiple Processes • Virtual cache support for multiple processes: • Flush the cache between each context switch. • Use processID (a unique number for each processes given by the operating system) as part of the tag

  31. Multiple Processors • Can run two programs at the same time • Each processor has its own cache. Why? • May or may not share data • Sharing code is not a problem (read only) • Example: shared libraries, DDLs • Sharing data (read/write) is a problem • What if it is in one processors cache? • Solution: Snoopy caches

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