1 / 72

Analog VLSI Design

Analog VLSI Design. Nguyen Cao Qui. Introduction to the course. Name: “ Analog VLSI Design ” Instructor: Nguyen Cao Qui email: ncqui@ctu.edu.vn Goals:

cade
Download Presentation

Analog VLSI Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Analog VLSI Design Nguyen Cao Qui

  2. Introduction to the course • Name: “ Analog VLSI Design ” • Instructor: Nguyen Cao Qui email: ncqui@ctu.edu.vn • Goals: The goal of this course is to introduce the principles of operation, design and technology of Analog Integrated Circuits to Electrical Engineering students at Senior level. VLSI technology and analog integrated circuit design is covered with an emphasis on CMOS Technology. CMOS layout design and analog simulation tools (Cadence) are demonstrated and used. Students will do a design project and final exam at the end.

  3. Introduction to the course • Number of credits : 3 (1: theory ; 2: homework + project +Seminar) • Textbooks: “CMOS: Circuit Design, Layout, and Simulation” R. Jacob Baker • Other Books: "CMOS Analog Circuit Design" Phillip E. Allen and Douglas R. Holdberg

  4. Introduction to the course • Course Policies: * Homework + Project : 40% * Final Test :60%

  5. CONTENTS • Chapter 1: Introduction to CMOS Design • Chapter 2: The Well • Chapter 3: The Metal Layers • Chapter 4: The Active and Poly Layers • Chapter 5: CAD Tools (Cadence) • Chapter 6: Resistors, Capacitors, MOSFETs • Chapter 7: Models for Analog Design • Chapter 8: The Inverter • Chapter 9: VLSI Layout Examples • Chapter 10: Current Mirrors • Chapter 11: Amplifiers • Chapter 12: Differential Amplifiers • Chapter 13: Operational Amplifiers I • Chapter 14: Voltage References • Chapter 15: Data Converter Fundamentals (ADC) • Chapter 16: Data Converter Fundamentals (DAC)

  6. Chapter 1Introduction to CMOS Design • CMOS (complementary metal oxide semiconductor) • CMOS is used in most very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) • "VLSI" : chips containing thousands or millions of MOSFETs. • "ULSI" : containing billions, or more, MOSFETs. • We focus simply on analog CMOS circuit design

  7. Introduction to CMOS Design 1. The CMOS IC Design Process

  8. The CMOS IC Design Process 1.1 Fabrication • CMOS integrated circuits are fabricated silicon wafers. • Each wafer contains chipsor "die" • The most common wafer size is 300 mm

  9. 2. CMOS Background • CMOS circuit design was invented in 1963 by Frank Wanlass • Circuit could be made with discrete complementary MOS devices, an NMOS and a PMOS NMOS PMOS

  10. 2. CMOS Background * Ex: CMOS Inverter

  11. 2. CMOS Background • Advantages of CMOS: • Low power • Layout on small area • Can be fabricated with few defects and low cost. 95% of ICs are fabricated in CMOS

  12. 3. Technology Scale Down * The Moore’s Law : Doubling every 18 months

  13. 3. Technology Scale Down

  14. Chapter 2: The Well * Studying the well to: • Understanding CMOS integrated circuit layout and design. • Understanding the performance limitations and parasitics. • Understanding the details of each fabrication (layout) layer.

  15. Chapter 2: The Well * The Substrate (The Unprocessed Wafer) • CMOS circuits are fabricated on and in a silicon wafer • N-type wafer: doping with donor atoms, exp: phosphorus • P-type wafer: doping with acceptor atoms, exp: boron • P-type wafer: the most common substrate used • NMOS are fabricated directly in the p-type wafer • PMOS are fabricated in an "n-well."

  16. Chapter 2: The Well * A Parasitic Diode

  17. Chapter 2: The Well * Using the N-well as a Resistor

  18. 2.1 Patterning CMOS integrated circuits are formed by patterning different layers on and in the silicon wafer.

  19. 2.1 Patterning

  20. 2.1 Patterning

  21. 2.1.1 Patterning the N-well

  22. 2.2 Laying Out the N-well

  23. 2.2.1 Design Rules for the N-well

  24. 2.3 Resistance Calculation

  25. 2.3 Resistance Calculation

  26. 2.3 Resistance Calculation * Layout of Corners

  27. 2.4. PN Junction Physics - Capacitance

  28. 2.4. PN Junction Physics - Capacitance

  29. 2.5. Design Rules for the Well

  30. Chapter 3: The Metal Layers • The metal layers: connect circuit elements (MOSFETs, capacitors, and resistors). • There are several metal layers when layout • These levels of metal are named metal1 (M1), metal2 (M2)…

  31. 3.1 The Bonding Pad • The interface between the die and the package

  32. 3.1.1 Laying Out the Pad

  33. Capacitance of Metal-to-Substrate

  34. Insulator - Overglass layer

  35. 3.2 Design and Layout Using the Metal Layers 3.2.1 Metal1 and Via1

  36. An Example Layout

  37. 3.2.2 Parasitics Associated with the Metal Layers

  38. Intrinsic Propagation Delay The velocity The delay of the metal line Where

  39. 3.2.3 Design Rules for the Metal Layers

  40. A Layout Trick for the Metal Layers

  41. 3.2.4 Contact Resistance

  42. 3.4 Layout Examples

  43. 3.4 Layout Examples

  44. 3.4 Layout Examples

  45. 3.4 Layout Examples

  46. 3.4 Layout Examples

More Related