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Chapter 7

Chapter 7. Designing Sequential Logic Circuits. Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03. Sequential Logic. Finite State Machine (FSM) Pipelined System. 2 storage mechanisms: Positive feedback (SRAM) Charge-based (DRAM). Naming Conventions. In our textbook:

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Chapter 7

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  1. Chapter 7 Designing SequentialLogic Circuits Rev 1.0: 05/11/03 1.1: 5/23/03 1.2: 5/30/03

  2. Sequential Logic • Finite State Machine (FSM) • Pipelined System • 2 storage mechanisms: • Positive feedback (SRAM) • Charge-based (DRAM)

  3. Naming Conventions • In our textbook: • a latch is Level-sensitive flip-flop • a register is Edge-triggered flip-flop • There are many different naming conventions • For instance, many books call Edge-triggered elements flip-flops (asynchronous JK, SR)  This leads to confusion

  4. Latch v.s. Register • Latch stores data when clock is low (or high) • Register stores data when clock rises (on edges) D Q D Q Clk Clk Clk Clk D D Q Q

  5. Latches transparent hold hold hold

  6. Latch-Based Design • N latch is transparentwhen f = 0; hold when f = 1 • P latch is transparent when f = 1; hold when f = 0 f f N P Logic Latch Latch Logic

  7. CLK Register t D Q t t su hold D DATA CLK STABLE t t c q - Q DATA STABLE t Timing Definitions • (a) Setup time (T_su): the time before the clock edge that the D input has to be stable • (b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable • (c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.

  8. Characterizing Timing t D -Q D Q D Q Clk Clk t t C -Q C -Q Latch Register

  9. Maximum Clock Frequency T CLK tclk-Q + tp,comb + tsetup Also: tcdreg + tcdlogic >= thold tcd: Contamination Delay = Minimum delay tclk-Q + tp,comb + tsetup <= T

  10. Q 0 Q 1 D 1 D 0 CLK Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK

  11. Mux-Based Latch

  12. Mux-Based Latch CLK Q M CLK Q M CLK CLK Non-overlapping clocks NMOS only

  13. CLK D D CLK Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Forcing the state (can implement as NMOS-only) Converting into a MUX

  14. Master-Slave (Edge-Triggered) Register Positive Latch Master Slave Negative Latch Two opposite latches trigger on edge Also called “master-slave latch Pair “

  15. I I T I I T I Q 5 2 2 3 5 4 6 Q M D I T I T 1 1 4 3 CLK Master-Slave Register Multiplexer-based latch pair

  16. Setup Time of MS-Register • I2-T2 : I2 output toT2 • Check input of T2 and output of T2 are the same

  17. Clk-Q Delay 2.5 CLK 1.5 D t c - q(lh) t c - q(hl) Volts Q 0.5 2 0.5 0 0.5 1 1.5 2 2.5 time, nsec

  18. Reduced Clock Load Master-Slave Register c.f: 8 Clock loads in Mater-Slave Register Design

  19. Avoiding Clock Overlap X CLK CLK Q A D B CLK CLK (a) Schematic diagram CLK CLK (b) Overlapping clock pairs

  20. NOR-based Set-Reset Flop-Flop S Q S R Q Q 0 0 Q Q S Q Q R 1 0 1 0 R Q 0 1 0 1 1 1 0 0 Forbidden State SR Flip-Flop: Cross-Coupled Pairs Cross-coupled NORs Cross-coupled NANDs

  21. S Q Q R Cross-coupled NORs Clocked NOR-based SR Flip-Flop Added Clock Control This asynchronous SR FF is NOT used in datapaths any more,but is a basic building memory cell

  22. Sizing Issues Output voltage dependence on transistor width Transient response

  23. CLK D Q CLK Storage Mechanisms Static Dynamic (charge-based)

  24. Clock Overlap T0-0: T1 and T2 on  Race Condition

  25. Making a Dynamic Latch Pseudo-Static Adding a weak feedback inverter

  26. Clocked CMOS (C2MOS) “Keepers” can be added to make circuit pseudo-static

  27. Insensitive to Clock-Overlap V V V V DD DD DD DD M M M M 2 6 2 6 M M 0 0 4 8 X X D Q D Q M M 1 1 3 7 M M M M 1 5 1 5 (a) (0-0) overlap (b) (1-1) overlap

  28. True Single-Phase Clocked Register (TSPC) Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) A register can be constructed by cascading Positive and Negative Latches  12 transistors are used!

  29. Including Logic in TSPC Example: logic inside the latch AND latch

  30. Pipelined TSPC CMOS System • Compared with NORA CMOS, we need two extra transistors per stage. But we can operate at a true singe-phase clock signal. • Very attractive from system-design point of view.

  31. Positive Edge-triggered Register in TSPC

  32. TSPC-based Positive Edge-Triggered DFF From Referenced Textbooks: [1] “CMOS Integrated Circuits: Analysis and Design,” 3rd Ed., by Sung-Mo Kang and Yusuf Leblebici, McGraw-Hill, 2003.

  33. Pipelined Systems using Dynamic CMOS Circuits

  34. Pipelining Pipelined Reference T_(non-pipe) = 3 x T_(pipeline)

  35. Pipelining At the expense of “Latency (input-to-output delay)”  Not good for interactive communicaitons

  36. Latch-Based Pipeline Be careful of Race! Hold G Hold F

  37. Review of NP-Domino Logic

  38. NP-Domino Logic Example

  39. NORA CMOS • Evaluation at Phi=1 • Evaluation at Phi=0 • Pipelined NORA CMOS system

  40. Latch-based Pipeline using C2MOS Race-free as long as function F (implemented by static logic) between the Latches are Non-inverting!

  41. Potential Race Condition during 0-0 (if F is inverting)

  42. Example of NORA-CMOS (I)

  43. Example of NORA-CMOS (II) NOR2 + INV = OR2 (Dynamic + Static Stages)

  44. Summary • Sequential circuits need good latches and registers for speed performance. • Dynamic circuits can realize the pipelined system in a very efficient and compact way. But it should be designed with extreme care. • Current trend is NOT to use dynamic CMOS for normal-speed operations  good for design, maintain, and verification.

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