Huang-Yu Chen † , Mei-Fang Chiang † , Yao-Wen Chang † Lumdo Chen ‡ , and Brian Han ‡

1. Novel Full-Chip Gridless Routing Considering Double-Via Insertion Huang-Yu Chen†, Mei-Fang Chiang†, Yao-Wen Chang† Lumdo Chen‡, and Brian Han‡ †The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan ‡UMC, Taiwan

2. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

3. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

4. metal 1 via metal 2 redundant via Redundant-Via Insertion • Via-open defects are one of the dominant failures due to the low-k, copper metal process in the nanometer era • Redundant-via insertion is highly recommended by foundries to improve via yield and reliability • Double vias have 10X 100X smaller failure rates than single vias double-via insertion 90nm copper interconnect (source: TSMC)

5. metal 1 via metal 2 Dead, Alive, and Critical Vias • For a via, a redundant-via candidate is its adjacent position where a redundant via can be inserted • Via categories: • Dead via: the via with no redundant-via candidate • Alive via: the via with at least one redundant-via candidate • Critical via: the via with exactly one redundant-via candidate critical via redundant-via candidate alive vias dead via

6. T T T S S S Redundant-Via Aware Routing • Traditionally, double-via insertion is focused on the post-layout stage • Minimizing dead and critical vias during routing can increase the post-layout double-via insertion rate by 15 25% • Dead vias cannot be paired with redundant vias • Critical vias may not be paired due to competition with others alive via dead via a routing instance a bad path a better path

7. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

8. Multilevel Routing • Billions of transistors may be fabricated in a single chip • Multilevel routing has demonstrated the superior capability of handling large-scale designs Already-routed net To-be-routed net ‧global routing ‧detailed routing ‧failed nets rerouting ‧refinement coarsening uncoarsening

9. Observations • In the coarsening stage, global and detailed routing are intertwined with each other at each level • Advantage: • Routing resource estimation is accurate • Information of previously routed nets is exactly known • Disadvantage: • Optimization freedom is limited • Refinement takes a lot of efforts and the solution easily falls into local optima Need more flexibility to address nanometer electrical effects

10. Ideas for Improvements • Separate global routing and detailed routing • Effectively perform global and detailed routing optimization • Pre-analyzecongestion to assist resource estimation • Apply bottom-up routing approaches to handle local circuit effects • Better for routability, congestion, and via minimization • Redundant-via planning is a local effect Maximize the optimization freedom

11. Our Two-Pass, Bottom-Up Routing Framework To-be-routed net Already-routed net G2 coarsening G2 coarsening G1 G1 coarsening G0 high coarsening G0 low Prerouting Stage First Pass Stage Second Pass Stage Identifycongestion hot spots based on the routing topology of each net Apply global routing for local nets and iteratively refine the solution Use detailed routing for local nets, reroute failed nets, and estimate resources level by level

12. Redundant-Via Aware Routing Congestion-Prediction Prerouting Via-Minimization Global Routing Redundant-Via Aware Detailed Routing

13. Congestion-Prediction Prerouting • Predict congestion hot spots to guide the following routing for better congestion minimization • Help to reduce detours and thus the via count • Alleviate post-layout double-via insertion efforts global tile routingtopology congestion-prediction prerouting congestion-minimization global routing

14. T T +3/5 +2/5 +1/5 +1/5 +1/5 +1/5 +2/5 +1/5 +1/5 +1/5 +1/5 +1/5 +2/5 +1/5 S +2/5 +1/5 +3/5 S Probabilistic Congestion Model • Predict congestions based on the probabilistic distribution of 1- and 2-bend global routes five 1- and 2-bend global routes • probabilistic congestions may become congestion hot spot

15. Via-Minimization Global Routing • Apply congestion-driven global pattern routing [TCAD’02] to reduce via counts • Uses L-shaped (1-bend) and Z-shaped (2-bend) connections to route nets • Has lower time complexity than maze routing L-shaped (1-bend) connection Z-shaped (2-bend) connection

16. Cost function for a net n: Vn: #via, Pn: redundant-via related penalty. Redundant-Via Aware Detailed Routing • The objective is to minimize dead and critical vias • Router should select a path that passes through the fewest redundant-via candidates in the routing graph • It may incur more detours and thus more vias • Must consider (1) redundant-via planning and (2) via minimization simultaneously • Take the via count and redundant-via related penalty as the cost to guide the detailed maze routing

17. T 1/4 1/4 1/4 1/3 1/4 S 1/2 1/3 1/2 1/3 Redundant-Via Related Penalty • Degree of Freedom of via v (DoFv): • # of redundant-via candidates of v • Set the cost of redundant-via candidate r as { max{ } | vi is the via that shares r } penalty = 1/4 ? T ? penalty = 5/6 S metal 1 metal 2 via redundant-via candidate

18. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

19. 2 vias are paired 3 vias are paired metal 1 via metal 2 redundant via Post-Layout Double-Via Insertion Problem • Given a post-routing layout, pair each via with one redundant via as many as possible without incurring any design-rule violation • Different approaches may affect the insertion result Better Yield

20. Previous Work • Yao et al.[GLSVLSI’05]mentioned that post-layout double-via insertion can be solved by maximum bipartite matching • Lee andWang[ASPDAC’06] showed that maximum bipartite matching formulation is incorrect for some cases • Lee andWang used maximum independent set (MIS) to solve the problem and applied heuristics to speed up MIS is NP-complete, high time complexity

21. v1 v2 v3 v1 v1 r1 v2 v2 r2 v1 v1 v3 v3 v2 v2 v3 v3 A Troublesome Example metal 1 metal 2 v1 metal 3 v2 v3 via12 via13 redundant-via candidate routing layout cross-section view V1 and V3 cannot be paired simultaneously (vertical design-rule conflict) V2 and V3 cannot be paired simultaneously (horizontal design-rule conflict)

22. v1 v2 v3 v1 v1 v1 v1 r1 r1 v1 v2 v2 v2 v2 r2 r2 v2 r1,2 v1 v1 v3 v3 v3 v3 v3 v2 v2 v3 v3 v1 r1 v2 r2 v3 Bipartite Graph Formulation Problem V1 and V3 cannot be paired simultaneously V2 and V3 cannot be paired simultaneously ? a bipartite formulation another bipartite formulation best result Infeasible Lack optimality

23. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Optimal Algorithm for up to 3 Routing Layers • On-Track/Stack Redundant-Via Enhancement • Two-Stage Double-Via Insertion (TDVI) Algorithm • Experimental Result • Conclusion

24. metal 1 v1 metal 2 v1 v2 v2 metal 3 via12 cross-section view via13 routing layout redundant-via candidate v2 v2 v1 v1 r2 r2 r r v1 v1 v3 v3 v2 v2 v2 v2 v1 is paired v2 is paired Our Bipartite Formulation • If stack via is treated as one unit via, the double-via insertion for designs with up to 3 layers can be optimally solved by maximum bipartite matching • A polynomial-time optimal algorithm for the restricted case • The troublesome example can be accurately formulated

25. Redundant-Via Candidates Alive Vias r2 r4 r5 r1 r7 r3 r2 r9 v1 r3 r4,5 r8 v2 r6 v3 r7,8 v2 r7 v3 r9 design-rule conflict between r7 and r8 final bipartite graph Optimal Algorithm for up to 3 Layers v1 Redundant-Via Candidates Alive Vias r1 r6 v2 r1 r8 r2 v1 r3 v3 r4 routing layout r5 v2 r6 r7 r8 v3 r9 initial bipartite graph metal 1 metal 2 via12 via23 metal 3 redundant-via candidate

26. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Optimal Algorithm for up to 3 Routing Layers • On-Track/Stack Redundant-Via Enhancement • Two-Stage Double-Via Insertion (TDVI) Algorithm • Experimental Result • Conclusion

27. off-track on-track Preference for On-Track/Stack Redundant Via • Redundant vias can be placed on-track or off-track. • If aredundant via is placed on the wire segment of its corresponding via, it is on-track; otherwise, it is off-track • Prefer on-track and stack redundant vias for double-via insertion • On-track redundant vias consume fewer routing resources • Better to protect stack vias which have lower yield than single vias v1 r1 metal 1 metal 2 r4 r2 metal 3 r3 r5 via12 via23 r6 redundant-via candidate v2 routing layout

28. stack redundant via preference tr/N, if v is a stack via containing N single vias; w(v,r) = tr, if v is a single via. on-track redundant via preference 1, if r is on-track; tr = 2, if r is off-track. On-Track/Stack Redundant-Via Enhancement • Construct the weighted bipartite graph and use minimum weighted bipartite matching to solve • For via v and its redundant-via candidate r, define weight w(v, r) as follows:

29. v1 v1 r1 r6 v2 v2 r1 r6 r2 r4 r5 r3 r8 r7 r9 r9 v3 v3 insertion result with preference metal 1 metal 2 Double-Via Insertion with Preference r1 1/2 1 r2 v1 1/2 r3 1 r4,5 2 1 v2 r6 2 2 r7,8 v3 2 r9 weighted bipartite graph routing layout metal 3 via12 via24 redundant-via candidate metal 4 via23 redundant via

30. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Optimal Algorithm for up to 3 Routing Layers • On-Track/Stack Redundant-Via Enhancement • Two-Stage Double-Via Insertion (TDVI) Algorithm • Experimental Result • Conclusion

31. r1 r2 r8 r5 r6 r3 r4 r7 conflict Two-Stage Double-Via Insertion Algorithm 1. Partition the layout into sublayouts with at most 3 layers, s.t. # of design-rule conflicts between sublayouts is minimized v1 v2 v5 Lt v6 Lb v3 v4 metal 1 metal 2 via metal 3 metal 4 redundant-via candidate

32. criticality = 0 criticality = 2 metal 1 metal 2 via metal 3 metal 4 redundant-via candidate Two-Stage Double-Via Insertion Algorithm 2. Decide the priority of each sublayout by criticality • For redundant-via candidate r that has design-rule conflicts with the different sublayout, criticality cr = # of induced dead vias after inserting r; otherwise, cr = 0 • Criticality of sublayout L = Σ cr, where r is inside L v1 r1 r2 v2 v5 Lt Criticality: 0 r8 r5 r6 v6 Lb Criticality: 2 v3 r3 r4 r7 v4 conflict

33. v1 r1 v2 r2 v3 r3 v4 r4,5 v5 r7,8 v6 metal 1 metal 2 via metal 3 metal 4 redundant-via candidate Two-Stage Double-Via Insertion Algorithm 3. Solve sublayouts in the non-decreasing order of criticality • If one sublayout is solved, update its adjacent sublayouts by removing the infeasible redundant-via candidates v1 r1 r2 v2 v5 Lt Criticality: 0 r8 r5 r6 v6 Lb Criticality: 2 v3 r3 r4 r7 v4 conflict

34. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

35. Experimental Setting • Platforms • Routing system: 1.2 GHz Sun Blade 2000 • Double-via insertion algorithm: 3.2 GHz Intel Pentium 4 • DRC verification: Cadence SoC Encounter • MCNC benchmark:

36. Gridless Routing Comparison • Compared with the gridless router • Reduce the via count 20% over MGR [ASPDAC’05] • Reduce the via count 24% over VMGR [ASPDAC’06]

37. Redundant-Via Aware Detailed Routing • Consider redundant vias during detailed routing • 1.4X fewer dead vias and 1.1X fewer critical vias • 2% slight increase in the via count

38. Post-Layout Double-Via Insertion • Compared with H3K [ASPDAC’06] • 71X runtime speedup • A higher insertion rate (98.6%) and a higher on-track rate (79.2%)

39. Double-Via Insertion of S5378

40. Local View of Insertion Results

41. Outline • Introduction • Redundant-Via Aware Two-Pass Routing System • Post-Layout Double-Via Insertion Algorithm • Experimental Result • Conclusion

42. Conclusion • We have developed a redundant-via aware gridless routing system • Reduced via counts • Obtained fewer dead vias and critical vias • We have proposed a post-layout double-via insertion algorithm • Resulted in a higher insertion rate • Resulted in a higher on-track rate • Achieved at least one-order runtime speedup

43. Thank You!

44. Q & A