CDR Introduction and Overview

1. CDR Introduction and Overview Paul Dauncey Imperial College London Paul Dauncey - CDR Introduction

2. Main aim of CALICE is a beam test • Electromagnetic (ECAL) and hadronic (HCAL) calorimeters • Final aim is for a linear collider after 2010 • Test prototypes in beam starting in mid 2004 • Several tests, running (not continuously) for around 1 year in total • UK proposal to build ECAL back-end readout electronics • Front-end electronics supplied by Orsay/Paris group • No proposals for HCAL back-end yet • Front-end not very firm but some effort there • Adapt ECAL readout electronics for HCAL back-end? • No proposals for trigger, beam monitoring, etc, either • Need to be flexible to accommodate uncertainties here Paul Dauncey - CDR Introduction

3. ECAL system • 11cm2 silicon diode pads, each diode is a channel • 18  18 diodes = 324 channels/layer • 30 layers = 9720 channels • Front-end electronics is VFE chips on VFE-PCB’s • 6 chips/PCB, 18 channels/chip and 108 channels/PCB • VFE chip is charge integrating amplifier with CR-RC shaper • Requires 14 bits dynamic range, 10 bits resolution • The 18 channels/VFE chip are multiplexed onto one output line as analogue voltages • Readout needs to digitise signal at peak = 180ns • VFE has calibration circuit to inject charge at input stage Paul Dauncey - CDR Introduction

4. VFE-PCB interface • Interface is at VFE-PCB connector • Time dependent signals through connector shown below • Sample-and-hold timing critical, needed to ~10ns • All others less severe, needed to ~100ns Paul Dauncey - CDR Introduction

5. Trigger interface • Trigger using scintillators in beam • Trigger logic not completely trivial • Need to hold off further triggers until each event read out • Need to be able to veto trigger if too close (~1ms) to last activity • Need to be able to abort trigger if activity soon (~100ns) after trigger • Need to know if beam present or not • Need several types of trigger (beam, cosmic, calibration, pedestal, etc.) selectable from DAQ • Also (potentially) need trigger fan-out to HCAL readout with adjustable delay • No proposal for a CALICE group to build this (yet) • Have to retain large degree of flexibility given uncertainties here • Some/all of logic could be built into readout/DAQ system Paul Dauncey - CDR Introduction

6. Data acquisition interface • Need to read all channels for every event • Could do threshold suppression in principle • Need to see pedestals and noise at least in some subsample • Allow for inclusion of HCAL, trigger and beam monitor • Event numbers required • Need around 200 set-ups (particle types, energies, HCAL options, entrance angles, etc.) • Need ~3105 events for each set-up • Total sample ~6107 events • Rates required to take these events in a reasonable time • Need around 100 Hz sustained rate • Given beam structure, this requires around 1kHz peak rate • Data sizes: event will be around 25 kBytes • Total data size around 1.5 TBytes Paul Dauncey - CDR Introduction

7. Proposed system • Cables from VFE-PCB’s direct to 15 VME readout boards • External trigger to 1 VME trigger board, then distributed via customised backplane • Also need a test board for debugging readout cards Paul Dauncey - CDR Introduction

8. HCAL implications • There are (at least) three HCAL options • Analogue readout: scintillating tiles, ~1500 channels • Digital readout: RPC’s or GEM’s, ~350k channels • Analogue option may use VFE chip (on different PCB) • Simple (in principle) to use same readout electronics • Not clear if all 18 channels/VFE chip used in this option • Minimum of 3 extra readout boards needed, maybe more • Digital options will share front-end readout • 38 layers, each with zero suppression at front-end • Expected total event size around 2kBytes • No proposal for back-end electronics; also use ECAL readout? • Basically need an LVDS I/O data path • Minimum of 7 extra readout boards needed, maybe more • Need to allow for multiple crates and at least two trigger boards Paul Dauncey - CDR Introduction

9. VME crate specifics • Customise crate for trigger and addressing • Use some of 64 spare pins on J2 • Four LVDS signals bussed on backplane • System clock (~12.5MHz) • Trigger • Two spares • Geographical slot addressing • Six TTL pins with unique value for each slot • Six bits are needed to cover two crates = 42 slots • Power supplies: need 3.3V rather than 5V • For LVDS I/O signals • FPGA’s run at 1.8V or 2.5V, stepped down from 3.3V • May be issue with non-UK readout (beam monitoring, etc)? Paul Dauncey - CDR Introduction

10. Summary • External interfaces are still in flux • VFE-PCB reasonably firm • Trigger and HCAL very uncertain • Basic system concept laid out here • Will have to react to changes in interfaces • Hopefully no major architectural changes needed • Following talks lay out proposed system in more detail • Readout and trigger board internals • Final talk will discuss cost, effort, schedule Paul Dauncey - CDR Introduction