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Based on slides from D. Patterson and www-inst.eecs.berkeley/~cs152/

COM 249 – Computer Organization and Assembly Language Chapter 4 The Processor. Based on slides from D. Patterson and www-inst.eecs.berkeley.edu/~cs152/. Introduction. §4.1 Introduction. Chapter 1 explained CPU performance factors Instruction count Determined by ISA and compiler

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Based on slides from D. Patterson and www-inst.eecs.berkeley/~cs152/

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  1. COM 249 – Computer Organization andAssembly LanguageChapter 4 The Processor Based on slides from D. Patterson and www-inst.eecs.berkeley.edu/~cs152/ Modified by S. J. Fritz Spring 2009 (1)

  2. Introduction §4.1 Introduction • Chapter 1 explained CPU performance factors • Instruction count • Determined by ISA and compiler • CPI and Cycle time • Determined by CPU hardware • Chapter 2 explained that the compiler and the instruction set architecture determine the instruction count for a program. • But - the implementation of the processor determines both the clock cycle time and the number of clock cycles per instruction. Modified by S. J. Fritz Spring 2009 (2)

  3. Introduction §4.1 Introduction • In this chapter we will construct the data path and the control unit for 2 different instruction set implementations • We will examine two MIPS implementations • A simplified version • A more realistic pipelined version • Simple subset, shows most aspects • Memory reference: lw, sw • Arithmetic/logical: add, sub, and, or, slt • Control transfer: beq, j Modified by S. J. Fritz Spring 2009 (3)

  4. Instruction Classes • In keeping with the principles of simplicity and making the common case fast, the actions are mostly the same for each of these classes of instructions: • Memory-reference • Arithmetic-logical • Branches • All classes except jump use the ALU after reading registers • After using the ALU, the actions differ Modified by S. J. Fritz Spring 2009 (4)

  5. Memory Reference • Memory-reference instructions use the ALU for an address calculation • It will need to access memory either to read data (load) or write data ( store). • Arithmetic-logical instructions use the ALU for operation execution • It must write the data from the ALU back into the a register • For a branch instruction, we may need to change the next instruction address based on the comparison; otherwise the PC is incremented by 4 to get the next instruction. Modified by S. J. Fritz Spring 2009 (5)

  6. Instruction Execution • Send the PC to the memory that contains the code and fetch the instruction • PC  instruction memory, fetch instruction • Read one or two registers • Register numbers register file, read registers • Depending on instruction class • Use ALU to calculate • Arithmetic result • Memory address for load/store • Branch target address • Access data memory for load/store • PC  target address or PC + 4 Modified by S. J. Fritz Spring 2009 (6)

  7. CPU Overview • High-level view focuses on the functional units and their interconnection. • Omits two important aspects of instruction execution: • It shows data coming form two separate sources, where in actuality it requires a logic element to choose; this is a multiplexor or a data selector (See Appendix C) • Several units must be controlled depending on the type of instruction ( e.g. data memory must read on a load and write on a store instruction) Modified by S. J. Fritz Spring 2009 (7)

  8. CPU Overview buses Modified by S. J. Fritz Spring 2009 (8)

  9. CPU Overview • PC sends instruction address to instruction memory • Instruction is fetched • Registers for the instruction are specified by fields in the instruction • Register operands are fetched • Operands used to compute an address or an arithmetic result or a compare in the ALU • Result of ALU is written to a register or memory (depending on the type of instruction) Modified by S. J. Fritz Spring 2009 (9)

  10. Multiplexors • Can’t just join wires together • Use multiplexers Modified by S. J. Fritz Spring 2009 (10)

  11. Control Unit • A control unit, which has the instruction as an input, is used to determine how to set the control lines for the functional units and for two multiplexors. • The third multiplexor, which determines whether the PC +4 or the branch destination address is written into the PC, is set based on the Zero output of the ALU, which is used to perform the comparison of a beq instruction • This simple decoding can be used to set all control lines. Modified by S. J. Fritz Spring 2009 (11)

  12. Control Modified by S. J. Fritz Spring 2009 (12)

  13. Logic Design Basics • Information encoded in binary • Low voltage = 0, High voltage = 1 • One wire per bit • Multi-bit data encoded on multi-wire buses • MIPS data path consists of 2 types of logic elements: • Combinational element • Operate on data • Output is a function of input ( given the same input always produces the same output) • State (sequential) elements • Store information ( e.g. memory and registers) §4.2 Logic Design Conventions Modified by S. J. Fritz Spring 2009 (13)

  14. A Y B A A Mux I0 Y + Y Y I1 ALU B B S F Combinational Elements • Adder • Y = A + B • AND-gate Y = A & B • Arithmetic/Logic Unit • Y = F(A, B) • Multiplexer • Y = S ? I1 : I0 Modified by S. J. Fritz Spring 2009 (14)

  15. Sequential (State) Elements • A state element has at least two inputs and one output: • Inputs: the data value to be written and the clock, which determines when the value will be written • Output: provides the value that was written in an earlier clock cycle • Example: D-type flip-flop, which has value and clock inputs and one output • State elements can be read at any time. • Called sequential because their output depend on both their inputs and the contents of their internal state • (See Appendix C) Modified by S. J. Fritz Spring 2009 (15)

  16. Signal Values • Asserted – a signal that is logically high or true or 1 • Assert specifies that a signal should be driven logically high • Deassert or deasserted represents a signal that is logically low or false or 0 Modified by S. J. Fritz Spring 2009 (16)

  17. Clocking Methodology • Defines when a signal can be read and when it can be written, or when it is relatively stable with respect to the clock • Designed to ensure predictability • Edge-triggered clocking – all state changes occur on a clock edge. • Allow us to read the contents of a register, send the value through some combinatorial logic and write the register in the same clock cycle • There is no feedback within a single clock cycle. Modified by S. J. Fritz Spring 2009 (17)

  18. D Q Clk Clk D Q Sequential Elements • Register: stores data in a circuit • Uses a clock signal to determine when to update the stored value • Edge-triggered: update when Clk changes from 0 to 1 Modified by S. J. Fritz Spring 2009 (18)

  19. Clk D Q Write Write D Clk Q Sequential Elements • Register with write control • Only updates on clock edge when write control input is 1 • Used when stored value is required later Modified by S. J. Fritz Spring 2009 (19)

  20. Clocking Methodology • Combinational logic transforms data during clock cycles • All signals propagate from state element 1to state element 2 in a single clock cycle • Between clock edges • Input from state elements, output to state element • Longest delay determines clock period Modified by S. J. Fritz Spring 2009 (20)

  21. Building a Datapath §4.3 Building a Datapath • Datapath • Elements that process data and addressesin the CPU • Registers, ALUs, mux’s, memories, … • We will build a MIPS datapath incrementally • Refining the overview design Modified by S. J. Fritz Spring 2009 (21)

  22. Datapath Elements • Memory unit – tostore the instructions of a programand supply instructions when given an address • Program counter (PC)- register that holds the address of the current instruction • Adder- to increment the PC to the address of the next instruction • Combinatorial • Built from the ALU by wiring the control lines to specify an add operation Modified by S. J. Fritz Spring 2009 (22)

  23. Instruction Fetch Increment by 4 for next instruction 32-bit register • Fetch instruction from memory • Increment the PC so that it point to the next instruction, 4 bytes later Modified by S. J. Fritz Spring 2009 (23)

  24. R- Format Instructions • R-type or arithmetic-logic instructions: • Read two registers • Perform an ALU operation on register contents • Write the result to a register • Includes add, sub,AND, OR and slt • The 32 general registers make up a register file, where any register can be read/written by specifying the number of the register. • R- format instructions will read two words and write one into the registers for each instruction. Modified by S. J. Fritz Spring 2009 (24)

  25. R-Format Instructions • For each data word to be read: • Input to the register file to specify the number of the register to be read • An output form the register file that carries the value read from the registers • To write to the registers, need two inputs: • To specify the register number to be written • To supply the data to be written to the register • Register number inputs are 5 bits wide to specify one of the 32 registers (25 = 32) Modified by S. J. Fritz Spring 2009 (25)

  26. R-Format Instructions • Read two register operands • Perform arithmetic/logical operation • Write register result Modified by S. J. Fritz Spring 2009 (26)

  27. A Zero B Zero Signal • If the zero signal out of the ALU is asserted (1), the two input values are equal. • It is used to test for equality ALU operation 4 Modified by S. J. Fritz Spring 2009 (27)

  28. Load/Store Instructions • Load/Store Instructions computer a memory address by adding the base register to the offset field in the instruction. • To load, the value read from memory is written to the register • To store, the value must be read from the register file • For these instructions, we will need the register file and the ALU as well as a unit tosign-extend the 16 bit offset field in the instruction to a 32-bit signed value and a data memory unit to read/write to it. Modified by S. J. Fritz Spring 2009 (28)

  29. Load/Store Instructions • Read register operands • Calculate address using 16-bit offset • Use ALU, but sign-extend offset • Load: Read memory and update register • Store: Write register value to memory Modified by S. J. Fritz Spring 2009 (29)

  30. Branch Instructions • The branch instruction has 3 operands: • two registers that are compared for equality, • and a 16 bit offset used to compute the branch target address. • Its form is beq $t1,$t2, offset • To compute the branch target address, add the sign extend offset field of the instruction to the PC + 4 (and shift two bits so that it is a word offset). • If the branch is not taken ( when the operands are not equal) the incremented PC should replace the current PC value ( just as for other instructions) Modified by S. J. Fritz Spring 2009 (30)

  31. Branch Instructions • Read register operands • Compare operands • Use ALU, subtract and check Zero output • Calculate target address • Sign-extend displacement • Shift left 2 places (word displacement) • Add to PC + 4 • Already calculated by instruction fetch Modified by S. J. Fritz Spring 2009 (31)

  32. Branch Instructions Justre-routes wires Sign-bit wire replicated Modified by S. J. Fritz Spring 2009 (32)

  33. Composing the Elements • First-cut data path does an instruction in one clock cycle • Each datapath element can only do one function at a time • Hence, we need separate instruction and data memories • Use multiplexors where alternate data sources are used for different instructions Modified by S. J. Fritz Spring 2009 (33)

  34. Creating a Single Datapath • We combine the individual components into a single datapath and add the control signals. • The simplest datapath attempts to execute all instructions in one clock cycle. • To do this, no resource can be used more than once per instruction, so any element needed more than once must be duplicated. • Therefore we need a separate memory for instructions and another for data. • To share between different instruction classes, we allow multiple connections to the input of an element, using a multiplexor and a control signal to select among the multiple inputs. Modified by S. J. Fritz Spring 2009 (34)

  35. Building a Datapath • The operations of arithmetic-logical (R-Type) instructions and memory instructions datapath are quite similar. • The differences are: • The arithmetic-logical instructions use the ALU with inputs from 2 registers • The memory instructions use the ALU to compute the address and the second input is the sign extend 16 bit offset field. • The value stored in the destination register comes from the ALU for an R-type instruction or the memory ( for a load instruction). Modified by S. J. Fritz Spring 2009 (35)

  36. R-Type/Load/Store Datapath Modified by S. J. Fritz Spring 2009 (36)

  37. Simplest Full Datapath • This simple datapath combines all the elements required by simple MIPS instructions and can execute these instructions (load, Store, ALU ops, and branch) in a single cycle). • The control unit is added to take inputs and generate a write signal for each state element, the selector control for each MUX, and the ALU control. Modified by S. J. Fritz Spring 2009 (37)

  38. Full Datapath Fig. 4.11 Modified by S. J. Fritz Spring 2009 (38)

  39. ALU Control • ALU used for • Load/Store: F = add (to compute address) • Branch: F = subtract • R-type: F depends on funct field • The ALU (appendix c) defines 6 combinations of 4 inputs: §4.4 A Simple Implementation Scheme Modified by S. J. Fritz Spring 2009 (39)

  40. ALU Control • Assume 2-bit ALUOp derived from opcode • Combinational logic derives ALU control • Don’t cares are xxxxxx Modified by S. J. Fritz Spring 2009 (40)

  41. 0 4 35 or 43 rs rs rs rt rt rt rd address address shamt funct 31:26 31:26 31:26 25:21 25:21 25:21 20:16 20:16 20:16 15:11 10:6 15:0 15:0 5:0 The Main Control Unit • Control signals derived from instruction R-type Load/Store Branch opcode always read read, except for load write for R-type and load sign-extend and add Modified by S. J. Fritz Spring 2009 (41)

  42. Datapath With Control Fig. 4.17 Modified by S. J. Fritz Spring 2009 (42)

  43. Datapath With Control • The input to the control unit is the 6 bit opcode field from the instruction. • The outputs of the control unit are • 3 1 bit signals that control the MUXs (RegDst, ALU SRc,and MemToReg) • 3 signals for controlling the reads and writes in the register file and data memory (RegWrite, MemRead, MemWrite) • 1 bit signal to determine when to branch (Branch) • 2 bit Control signal for the ALU (ALUOp) • An AND gate combines the branch control signal and the Zero output from the ALU Modified by S. J. Fritz Spring 2009 (43)

  44. R-Type Instruction Fig. 4.19 Modified by S. J. Fritz Spring 2009 (44)

  45. Components Involved In Executing An R-Type Instruction Modified by S. J. Fritz Spring 2009 (45)

  46. Execution Stepsfor an R-Type Instruction • Four steps: • Fetch the instruction, add 4 to the PC value. • Send the operand register contents to the main ALU. • Perform the main ALU operation. • On the rise of the clock: • ALU result is stored in register file, and • Incremented PC value (from Step 1) is stored in the PC. • Change in the PC’s value initiates the next instruction fetch. Modified by S. J. Fritz Spring 2009 (46)

  47. Control Signalsfor an R-Type Instruction • Control signals are generated: • By control circuits (to be added to data path diagram) • From opcode/function bits of instructions. • Signal values for correct execution of R-Type instructions: • RegDst = 1 • RegWrite= Asserted • ALUSrc = 0 • MemWrite= Deasserted • MemtoReg = 1 • PCSrc= 0 Modified by S. J. Fritz Spring 2009 (47)

  48. Load Instruction Fig. 4.20 Modified by S. J. Fritz Spring 2009 (48)

  49. Relevant Signal Propagation Involved In Executing A lw Instruction write Modified by S. J. Fritz Spring 2009 (49)

  50. Relevant Signal Propagation Involved In Executing A sw Instruction write Modified by S. J. Fritz Spring 2009 (50)

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