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2013 CAD Contest Technology Mapping for Macro Blocks

2013 CAD Contest Technology Mapping for Macro Blocks. Team: WCYLab -Bach Ching -Yi Huang, Wei-An Ji , Yu-Min Chou, Zheng -Shan Yu Date: 2013/9/9. Outline. Problem Formulation Framework & Flow Logical macro mapping Continuous AND/NAND/OR/NOR/XOR/XNOR Arithmetical macro mapping Adder

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2013 CAD Contest Technology Mapping for Macro Blocks

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  1. 2013 CAD Contest Technology Mapping for Macro Blocks Team: WCYLab-Bach Ching-Yi Huang, Wei-An Ji, Yu-Min Chou, Zheng-Shan Yu Date: 2013/9/9

  2. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

  3. Problem Formulation

  4. Framework (I/O) ABC D D.blif Mapping ABC D’.blif D’.v Library VTR L.blif

  5. design.v lib.v Verilog Parser blif AIG Resyn2 Optimize NMG+NAR Yes 1. node# decrease? Continuous AND OR map No Algorithm 2. Adder 3. Mux 4. K cut Lazy man Output Standard cell mapping Out.v

  6. Framework & Flow • Classify the libraries into two categories • For logical macro blocks • Search for continuous AND/NAND/OR/NOR • Search for continuous XOR/XNOR • For arithmetic macro blocks • Adders • Mux • Others • Partition the multi-PO circuit into single-PO TFICs • Only deal with the K-cuts sub-circuits, where K < 13 • Map the cuts using Lazy Man’s method • Greedily cut & match the macros • Standard cell technology mapping • Transform the AIG to the normal gate-level circuit • Isolate the mapped macro blocks at the same time

  7. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

  8. Continuous AND Gates • Use DFS to do the searching in the netlist • Consider • No fanout in the cone • Maximum input number of the macro PI-1 DFS Target PI-2

  9. XOR/XNOR Gate • Brute-force analysis • 2 structures for XOR (with I/O phases) • 2 structures for XNOR (with I/O phases)

  10. Continuous XOR gates • How to record? • Super gate • Consider I/O phases DFS Save as super gate Union & Save

  11. Adder2 Sum Cout HA HA Truth Table Sum Cout 3-cut HA

  12. Adder2 3-bit Adder Cin Truth Table Cin Cout Sum Cout 3-cut

  13. (A0 A2) + (A1 A2) A0 xnor A1 (A0+A1) xor A2 A1’

  14. A0’ 1 0 A0 1 A1’ xor A0 = A1 xnor A0 A1’A0+A1 = (A0+A1) 0 A2 xor (A0+A1) A2 and (A0+A1) = A0A2+A1A2 A3 xor (A0A2+A1A2) = A3’(A0A2+A1A2)+A3(A0A2+A1A2)’ 0 A3 and (A0A2+A1A2)

  15. Adder 0 HA Cout 0 0 0 0

  16. Adder A0 B0 . . An Bn 0 0 A0 B0 . An Bn 0 0 True Full Adders Sum0~n Cout Sum0~n Cout Structural gate reusing by (0,1) insertion A0 1 A1 0 0 0 A0 1 A1 1 A2 0 0 0 Sum0~1 Cout Sum0~2 X A0 B0 0 0 A0 B0 0 0 Only Half Adders Sum0 Cout Sum0 X

  17. Adder3A+B+C structure (5 cut + 2 couts) Sum Cout1 Cout2 Sum Cout1 Cout2 Cin2 Cin1 Cin1 Sum Cout1 Cout2 Hard to find !!! By Gan-Gan 5-cut

  18. 4-bit Adder3 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 + + A3 +B3 A2 +B0 A1 +B1 A0 +B0 A3 +B3 A2 +B2 A1 +B1 A0 +B0 HA +C3 +C2 +C1 +C0 +C3 +C2 +C1 +C0 FA FA FA HA Good try!!! By Gan-Gan

  19. Adder3 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 1.Find out 3-cut adder2 + + + + + A3 +B3 A2 +B0 A1 +B1 A0 +B0 HA +C3 +C2 +C1 +C0 + + + + + +

  20. Adder3 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 2.Search for the SUM connection + + + + + A3 +B3 A2 +B0 A1 +B1 A0 +B0 HA +C3 +C2 +C1 +C0 + + + Consider cout connection A3 +B3 A2 +B0 A1 +B1 A0 +B0 + + + HA +C3 +C2 +C1 +C0

  21. Adder3 3. Determine the head/tail A B A B A B C A B C A B C 0 0 0 0 0 0 Adder3 Sum 0 + + + + + + Sum 1 Sum 2 C C C + + + + + + X X A B 4. Check the final adder A B C A B C A B C 0 0 0 0 0 0 Adder3 A B A B Sum 0 + + + Sum 1 + + + Sum 2 HA C C C Sum=Cout0 + + + + + + Sum= Cout1 A B

  22. Adder3 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 1.Find out 3-cut adder2 + + + + + A3 +B3 A2 +B0 A1 +B1 A0 +B0 HA +C3 +C2 +C1 +C0 + + + + + + +

  23. Adder3 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 2.Search for the SUM connection + + + + + A3 +B3 A2 +B0 A1 +B1 A0 +B0 HA +C3 +C2 +C1 +C0 + + + + Consider cout connection A3 +B3 A2 +B0 A1 +B1 A0 +B0 + + + HA +C3 +C2 +C1 +C0

  24. Adder3 3. Determine the head/tail A B A B A B C A B C A B C 0 0 0 0 0 0 Adder3 Sum 0 + + + + + + + Sum 1 Sum 2 C C C + + + + + + X X A B 4. Check the final adder A B C A B C A B C 0 0 0 0 0 0 Adder3 A B A B Sum 0 + + + + Sum 1 + + + Sum 2 HA C C C Sum=Cout0 + + + + + + Sum= Cout1 A B

  25. Adder3 3. Determine the head/tail Cin 1 0 A B C A B C 0 0 0 0 0 0 Adder3 X Sum 0 + + + + + + Sum 1 X + + + + + + Cin X Cin 1 1 Cin 2 A B C 0 0 0 0 0 0 Adder3 Sum 0 + + + + + + Sum 0 Cin1 X + + + + + + Cin2 X

  26. Adder3 A B A B 0 0 Cout 1 A B A B Adder3 Sum 0 A B A B 0 0 Cout 1 A B A B Adder3 Sum 0 Sum 1 Sum 1 + + + + Cout X Sum 2 Sum 2 Sum 3 Sum 3 A B C A B C 0 0 0 0 0 0 0 1 Cout1 A B 0 A B 0 Adder3 Sum 0 Cout1 Sum 1 + + + + X X + + X Sum 1

  27. Adder3 Cout1 Adder3 + + + + + + + Cout2 Cout Adder3 + + + + + +

  28. 4-bit Adder4 A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0 Adder2 Connection for Adder3 Connection for Adder4 + A3 +B3 A2 +B0 A1 +B1 A0 +B0 FA HA +C3 +C2 +C1 +C0 XOR HA +D3 +D2 +D1 +D0

  29. Mux • 4-bit mux 3 In1[0] In1[1] 2 4 In2[0] 1 In2[1] In2[2] Hard to find !!! By Yu-Min In2[3]

  30. Mux A B C MUX F 3-cut map

  31. Multiplier 0 A2 A1 A0 B3 0 0 B0 × 0 A2B0 A1B0A0B0 0 A2B3 A1B3A0B3 3. Check connection B0 B3 A A

  32. Isolation between macros and other standard cells • Trick Macro Macro PPOs PPIs

  33. Future work • Complete integration (almost) • Improvement (adder3, adder4, multiplier)

  34. Continuous NAND/OR/NOR Gates • Use DFS and Disjoint Set to do the searching in the netlist • Consider the locations of inverters Cont. NAND Cont. OR Cont. NOR Target Target Target PI-1

  35. Issue • Fanout-reconverge Target

  36. Issue • Fanout-reconverge Target

  37. Issue • Fanout-reconverge Target

  38. Issue • Fanout-reconverge PI-1 Target n1 n2 PI-2

  39. Issue • Fanout-reconverge • Duplicate PI-1 n1 n2 PI-2

  40. Issue • Fanout-reconverge • Duplicate PI-1 Target PI-1 n1 n2 PI-2

  41. XOR/XNOR Gate • Brute-force analysis • 3 structures for XOR • 3 structures for XNOR

  42. Continuous XOR gates • How to record? • Super gate & DFS & Disjoint Set DFS Save as super gate Union & Save

  43. Issue • Cont. AND vs. Cont. OR/NOR/NAND • If only 1 library appears – no problem • If both appear ? • AND or NOR? • Overlaps between XOR and cont. AND/… ? Target

  44. Outline • Problem Formulation • Framework & Flow • Logical macro mapping • Continuous AND/NAND/OR/NOR/XOR/XNOR • Arithmetical macro mapping • Adder • Others • Framework • Cutting • Matching • Progress & Future Work

  45. Two direction of mapping • True macros • Gate reusing

  46. Adder 0 • Full adder • structural mapping 1 7 1 1 8

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