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EE345: Introduction to Microcontrollers Synchronous Sequentional Logic

EE345: Introduction to Microcontrollers Synchronous Sequentional Logic. Prof. Ahmad Abu-El-Haija. Acknowledgement. This presentation is a modified version of lecture notes prepared by Dr. Nader Mohamed, Stevens Institute of Technology, and original slides from the publisher. Contents.

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EE345: Introduction to Microcontrollers Synchronous Sequentional Logic

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  1. EE345: Introduction to MicrocontrollersSynchronous Sequentional Logic Prof. Ahmad Abu-El-Haija

  2. Acknowledgement • This presentation is a modified version of lecture notes prepared by Dr. Nader Mohamed, Stevens Institute of Technology, and original slides from the publisher. Digital System Design

  3. Contents • Sequential Circuits • Storage Elements: Latches • Storage Elements: Flip-Flops • Analysis of Clocked Sequential Circuits • State Reduction and Assignment • Design Procedure EE345 - Introduction to Microcontrollers

  4. Sequential Circuits • The inputs and present state of the storage elements determine the value of the outputs. • The next state of the storage elements is also a function of external inputs and the present state. EE345 - Introduction to Microcontrollers

  5. Two Types of Sequential Circuits: Their classification depends on the timing of their signals. • Synchronous sequential circuit: its behavior can be defined from the knowledge of its signals at discrete instants of time. • Asynchronous sequential circuit: its behavior depends upon the input signals at any instant of time and the order in which the inputs change. Storage elements are used as time-delay devices. EE345 - Introduction to Microcontrollers

  6. Synchronous Clocked Sequential Circuit • A synchronous sequential circuit employs signals that affect the storage elements only at discrete instants of time. • Synchronization is achieved by a clock generator that provides periodic clock pulses. • Clock pulses are distributed throughout the digital system in such a way the storage elements are affected only with the arrival of each pulse. • Storage elements are called flip-flops. EE345 - Introduction to Microcontrollers

  7. Synchronous Clocked Sequential Circuit Synchronous Clocked Sequential Circuit EE345 - Introduction to Microcontrollers

  8. Storage Elements: Latches • A flip-flop circuit can maintain a binary state. • There are different types of flip-flops. • Basic type of flip-flops are Latches. • Latches are basic circuits from which all types of flip-flops are constructed. • Latches are used more in asynchronous sequential circuits. EE345 - Introduction to Microcontrollers

  9. SR Latch • The SR Latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, as will be explained next. EE345 - Introduction to Microcontrollers

  10. SR Latch with NOR Gates • SR Latch has two useful states: • Set state: when output Q=1 and Q’=0, and • Reset state: when output Q=0 and Q’=1. • These states can be used to store 1-bit information. Output Q and Q’ are normally complement of each other. • Undefined state: when Q=0 and Q’=0, occurs when both inputs R and S are equal to 1 at the same time. EE345 - Introduction to Microcontrollers

  11. SR Latch with NOR Gates • Under normal conditions, both inputs of the latch (R and S) remain at 0 unless the state has to be changed. • To let latch in the set state, S must be 1 • To let latch in the reset state, R must be 1 • The inputs S and R must go back to 0 before any other changes, to avoid the occurrence of the undefined state. • The latch goes to the set state or reset state and stays there, even after both inputs return to 0. EE345 - Introduction to Microcontrollers

  12. SR Latch with NOR Gates • When both inputs Sand Rare equal to 0, the latch can be in either the set or the reset state, depending on which input was most recently a 1. EE345 - Introduction to Microcontrollers

  13. SR Latch with NAND Gates As before, the SR Latch has two useful states: • Set state: when output Q=1 and Q’=0. • Reset state: when output Q=0 and Q’=1. Output Q and Q’ are normally complement of each other. • Undefined state: when Q=1 and Q’=1, occurs when both inputs R and S are equal to 0 at the same time. EE345 - Introduction to Microcontrollers

  14. SR Latch with NAND Gates • Under normal conditions, both inputs of the latch (R and S) remain at 1 unless the state has to be changed. • To let latch in the set state, S must be 0 • To let latch in the reset state, R must be 0 • The inputs S and R must go back to 1 before any other changes to avoid the occurrence of the undefined state (when Q=1 and Q’=1) • The latch goes to the set state or reset state and stays there, even after both inputs return to 1. EE345 - Introduction to Microcontrollers

  15. SR Latch with NAND Gates • When both inputs S and R are equal to 1, the latch can be in either the set or the reset state, depending on which input was most recently a 0. • Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an S’R’ latch. EE345 - Introduction to Microcontrollers

  16. SR Latch with Control Input • An indeterminate condition occurs when all three inputs are equal to 1. It is difficult to ensure that both S and R are not equal to 1 at the same time. • Operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. EE345 - Introduction to Microcontrollers

  17. D Latch (Transparent Latch) • D latch has only two inputs D (Data) and En (Enable). This circuit ensures that inputs S and R are never equal to 1 at the same time. EE345 - Introduction to Microcontrollers

  18. Graphic Symbols for Latches • Designated by a rectangular block. • Normal output and complemented output (bubble) • For NAND gates latch, set and reset by logic zero, hence the bubbles and bars at inputs. EE345 - Introduction to Microcontrollers

  19. Problems with Latches • State transitions of the latches start as soon as the clock pulse changes to logic 1 level. • The new state of a latch appears at the output while the pulse is still active. • Combinational circuit will generate new outputs and the state of the latch will change again within the same clock cycle. EE345 - Introduction to Microcontrollers

  20. Storage Elements: Flip-Flops • State of a latch or flip-flop is switched by a change in the control input. The momentary change is called a trigger, and transition it causes is said to trigger the flip-flop. • The problem with the latch is that it responds to a change in the level of a clock pulse. • A clock pulse goes through two transitions: from 0 to 1, and returns from 1 to 0. • The Solution: by changing the operation of a flip-flop to trigger it only during a single transition. • Two types of transitions: the positive transition and the negative transition. EE345 - Introduction to Microcontrollers

  21. Flip-Flops EE345 - Introduction to Microcontrollers

  22. Edge-Triggered D Flip-Flops • Master-Slave D Flip-Flop (Negative-edge-triggered flip-flop) • The circuit stores D in the master latch when CLK=1 and changes its output Q only at the negative-edge of the controlling clock. EE345 - Introduction to Microcontrollers

  23. D-Type Positive-Edge-Triggered Flip-Flop If CLK=0 → S=1 and R=1 (present state). If D=0 and CLK=1 → R changes to 0 (the reset state) If there is a change in D while CLK=1 → R remains at 0 (the flip-flop is unresponsive to further changes in the input). If CLK=0 → S=1 and R=1 (present state) If D=1 and CLK=1 → S changes to 0 (set state) If there is a change in D while CLK=1 → S remains at 0 (the flip-flop is unresponsive to further changes in the input). EE345 - Introduction to Microcontrollers

  24. D-Type Positive-Edge-Triggered Flip-Flop • When the input clock is in the positive-edge-triggered flip-flop, the value of D is transferred to Q. • The output Q is not affected: • During transition of CLK from 1 to 0. • When CLK is in the steady logic 1 level. • When CLK is in the logic 0 level. • Characteristic Equation: Q(t+1) = D EE345 - Introduction to Microcontrollers

  25. Edge Triggered D Flip-Flops Two types: • Master-Slave D Flip-Flop (Negative-edge-Triggered) • D-Type Positive-Edge-Triggered Flip-Flop Advantages: • Requires small number of gates to construct. • Can be used to construct other types of flip-flops. EE345 - Introduction to Microcontrollers

  26. J-K Flip-Flop • Two Inputs: J and K • Three Operations: • Set • Reset • Complement • Q(t+1) = JQ’+ K’Q EE345 - Introduction to Microcontrollers

  27. T Flip-Flop One Input: T D = T ⊕ Q=TQ’+T’Q Q(t+1) = TQ’+T’Q EE345 - Introduction to Microcontrollers

  28. Flip-Flop Characteristic Tables EE345 - Introduction to Microcontrollers

  29. Flip-Flop Characteristic Equations D FF: Q(t+1) = D JK FF: Q(t+1) = JQ’+ K’Q T FF: Q(t+1) =T⊕Q = TQ’+T’Q EE345 - Introduction to Microcontrollers

  30. Direct Inputs • Some flip-flop have asynchronous inputs that are used to force the flip-flop to a particular state independent of the clock. This operation is used for initialization. • The input that sets the flip-flop to 1 is called preset or direct set. • The input that clears the flip-flop to 0 is called clear or direct reset. • For a positive-edge-triggered D ff with asynchronous reset, when R=0, the output is reset to 0. This state is independent of the values of D or C. Normal clock operation can proceed only after the reset input goes to logic 1. EE345 - Introduction to Microcontrollers

  31. Positive-Edge-Triggered D FF with Asynchronous Reset EE345 - Introduction to Microcontrollers

  32. Synchronous Sequential Logic • Analysis of a sequential circuit: a circuit diagram a state table or state diagram • Design of a sequential circuit: a set of specifications a logic diagram EE345 - Introduction to Microcontrollers

  33. Analysis of Clocked Sequential Circuits Algebraic Expressions: A(t+1)=A(t)x(t)+B(t)x(t) B(t+1)=A’(t)x(t) A(t+1)=Ax+Bx B(t+1)=A’x y(t)=[A(t)+B(t)]x’(t) y=(A+B)x’ EE345 - Introduction to Microcontrollers

  34. State Table • State table for the circuit in the previous slide. EE345 - Introduction to Microcontrollers

  35. State Table & State Diagram States are represented by circles and the transitions between states are indicated by directed lines connecting the circles. EE345 - Introduction to Microcontrollers

  36. Flip-Flop Input Equations DA= Ax + Bx DB= A’x y = (A+B)x’ We have D flip-flops: Q(t+1) = DQ A(t+1) = Ax + Bx B(t+1) = A’x EE345 - Introduction to Microcontrollers

  37. Analysis with D Flip-Flops DA= A⊕x⊕y A(t+1) = DA A(t+1) = A⊕x⊕y EE345 - Introduction to Microcontrollers

  38. Analysis with JK Flip-Flops JA = B KA = Bx’ JB = x’ KB = A’x+Ax’ = A⊕x We have Q(t+1) = JQ’+K’Q A(t+1) = JAA’+KA’A = BA’+(Bx’)’A = A’B+AB’+Ax B(t+1) = JBB’ + KB’B =x’B’+(A⊕x)’B =B’x’+ABx+A’Bx’ EE345 - Introduction to Microcontrollers

  39. Analysis with JK Flip-Flops EE345 - Introduction to Microcontrollers

  40. Analysis With T Flip-Flops Characteristic equation: Q(t+1) = T⊕Q = T’Q+TQ’ TA = Bx , TB = x , y = AB A(t+1) = (Bx)’A + (Bx)A’ = AB’ + Ax’ + A’Bx B(t+1) = x ⊕ B EE345 - Introduction to Microcontrollers

  41. State Reduction and Assignment State-reduction problem: the process of reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirement unchanged. A sequential circuit with m flip-flops has 2m states. A reduction in the number of states may (or may not) result in a reduction in the number of flip-flips. EE345 - Introduction to Microcontrollers

  42. State Reduction Assume circuit is in state a, and let the input sequence be 01010110100. The complete input/output sequence: State a a b c d e f f g f g a Input 0 1 0 1 0 1 1 0 1 0 0 Output 0 0 0 0 0 1 1 0 1 0 0 EE345 - Introduction to Microcontrollers

  43. State Reduction Definition: Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state. • Algorithm for the state reduction: • Find the completely specified state table for the circuit. • When two states are equivalent, one of them can be removed • When the removed states are used in the next-state columns, change them with the equivalent state symbols. EE345 - Introduction to Microcontrollers

  44. State Reduction States g and e are equivalent: States d and f are equivalent: EE345 - Introduction to Microcontrollers

  45. State Reduction Same output sequence results, although state sequence is different. Reduced State Diagram From reduced state diagram From original state diagram EE345 - Introduction to Microcontrollers

  46. State Assignment State assignment: process of assigning coded binary vales to the states. EE345 - Introduction to Microcontrollers

  47. Design Procedure Set of specifications a logic diagram The procedure: 1. From the word description and specifications of the desired operation, derive a state diagram for the circuit. 2. Reduce the number of states if necessary. 3. Assign binary values to the states. 4. Obtain the binary-coded state table. 5. Choose the type of flip-flops to be used. 6. Derive the simplified flip-flop input equations and output equations (combinational circuit design). 7. Draw the logic diagram. EE345 - Introduction to Microcontrollers

  48. Synthesis Using D Flip-Flops Design a circuit that detects three or more consecutive 1’s in a string of bits coming through an input line. Use D ff’s. 1. State Diagram for Sequence Detector: (We will implement a Moore model sequential circuit) EE345 - Introduction to Microcontrollers

  49. Synthesis Using D Flip-Flops 2. Reduce the number of states if necessary. N/A here. 3. Assign binary values to the states. S0=00, S1=01, S2=10, and S3=11. 4. Obtain the binary-coded state table. EE345 - Introduction to Microcontrollers

  50. Synthesis Using D Flip-Flops 5. Choose the type of flip-flops to be used. We will use D flip-flops. We need two flip-flops. 6. Derive the simplified flip-flop input equations and output equations. A(t+1) = DA B(t+1) = DB EE345 - Introduction to Microcontrollers

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