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Pertemuan 11 Mesin Motorola 68000: I

Pertemuan 11 Mesin Motorola 68000: I. Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1. Learning Outcomes. Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu :

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Pertemuan 11 Mesin Motorola 68000: I

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  1. Pertemuan 11Mesin Motorola 68000: I Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  2. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer Motorola ( C4 ) ( No TIK : 5 )

  3. Chapter 3. Motorola Instruction Set: I

  4. MO VE.L N,D1 N con tains n , the n um b er of en tries to b e added, and D1 is used as a coun ter that determines ho w many times to execute the lo op. MO VEA.L #NUM1,A2 A2 is used as a p oin ter to the list en tries. It is initialized to NUM1, the address of the first en try . CLR.L D0 D0 is used to accum ulate the sum. LOOP ADD.W (A2)+,D0 Successiv e n um b ers are added in D0. SUBQ.L #1,D1 Decremen t the coun ter. BGT LOOP If [D1]  0, execute the lo op again. MO VE.L D0,SUM Store the sum in SUM. Figure 3.25. A 68000 program for the addition program in Figure 2.16.

  5. – MO VE.L N,D1 Put n 1 in to the SUBQ.L #1,D1 coun ter register D1. MO VEA.L #NUM1,A2 CLR.L D0 LOOP ADD.W (A2)+,D0 –1. DBRA D1,LOOP Loop bac k un til [D1]= MO VE.L D0,SUM Figure 3.26. An alternative 68000 program for the program in Figure 3.25.

  6. Memory Addressing address or data lab el Op eration information Assem bler directiv es C EQU $202200 OR G $201150 A DC.W 639 – B DC.W 215 OR G $201200 Statemen ts that MO VE A,D0 generate mac hine ADD B,D0 instructions MO VE D0,C Assembler directiv e END Figure 3.23. 68000 assembly language representation for the routine in Figure 3.22.

  7. T ABLE C.1 Address field encoding for 68000 Address field Mo de Register 5 4 3 2 1 0 Mode Addressing mode field Register field Data register direct 000 Register n um b er Address register direct 001 Register n um b er Address register indirect 010 Register n um b er Autoincrement 011 Register n um b er Auto decrement 100 Register n um b er Indexed basic 101 Register n um b er Indexed full 110 Register n um b er Absolute short 111 000 Absolute long 111 001 Relative basic 111 010 Relative full 111 011 Immediate or status register 111 100

  8. T ABLE C.2 Differences from Motorola terminology T erminology used in this book Motorola terminology Autoincrement Address register indirect with p ostincrement Auto decrement Address register indirect with predecrement Indexed basic Address register indirect with displacement Indexed full Address register indirect with index Relative basic Program coun ter with displacement Relative full Program coun ter with index

  9. T ABLE C.3 Notation for Table C.4 Symbol Meaning s Source operand d Destination operand An Address register n Dn Data register n Xn An address or data register, used as an index register PC Program counter SP Stack pointer SR Status register CCR Condition co de flags in SR AAA Address register n umber DDD Data register n umber rrr Source register n umber RRR Destination register n umber eeeeee Effective address of the source op erand EEEEEE Effective address of the destination op erand MMM Effective address mo de of destination CCCC Specification for a condition co de test P. . . P Displacement Q. . . Q Quick immediate data    SS Size: 00 b yte, 01 w ord, 10 long w ord (for most instructions)    01 b yte, 11 w ord, 10 long w ord (for MO VE and MO VEA instructions) VVVV T rap v ector n umber u Condition co de flag state is undefined (meaningless) d(An) Indexed basic addressing mode d(An,Xi) Indexed full addressing mode d(PC) Relative basic addressing mode d(PC,Xi) Relative full addressing mode

  10. T ABLE C.5 68000 branch instructions Mnemonic Displacement Operation (Name) size OP co de performed  BRA 8 0100 0000 PPPP PPPP PC [PC] disp + (Branch alw a ys) 16 0110 0000 0000 0000 PPPP PPPP PPPP PPPP Bcc 8 0110 If cc is true, then CCCC PPPP PPPP (Branch  conditionally) 16 0110 CCCC 0000 0000 PC [PC] disp + PPPP PPPP PPPP PPPP –  BSR 8 0110 0001 PPPP PPPP SP [SP] 4;  (Branch to [SP] [PC];  subroutine) 16 0110 0001 0000 0000 PC [PC] disp + PPPP PPPP PPPP PPPP DBcc 16 0101 CCCC 1100 1DDD If cc is false, then –  (Decremen t PPPP PPPP PPPP PPPP Dn [Dn] 1; –  and branc h If [Dn] 1, then  conditionally) PC [PC] disp + DBRA The assem bler in terprets this instruction as DBF (Decremen t (see the DBcc en try). and branc h)

  11. T ABLE C.6 Condition codes for Bcc, DBcc and Scc instructions Machine Condition code suffix CCCC cc Name Test condition 0000 T T rue Alw a ys true 0001 F F alse Alw a ys false  0010 HI High C Z = 0  0011 LS Lo w or same C Z = 1 0100 CC Carry clear C = 0 0101 CS Carry set C = 1 0110 NE Not equal Z = 0 0111 EQ Equal Z = 1 1000 V C Ov erflo w clear V = 0 1001 VS Ov erflo w set V = 1 1010 PL Plus N = 0 1011 MI Min us N = 1  1100 GE Greater or equal N V = 0  1101 L T Less than N V = 1   1110 GT Greater than Z (N V) = 0   1111 LE Less or equal Z (N V) = 1 T and F suffices cannot b e used in the Bcc instruction

  12. Pertemuan 12Mesin Motorola 68000: II Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1

  13. Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : • Membandingkan implementasi instruksi mesin untuk Arsitektur Komputer Motorola ( C4 ) ( No TIK : 5 )

  14. Chapter 3. Motorola Instruction Set: II

  15. MO VEA.L #LOC,A1 Initialize p oin ter register A1 to con tain the address of the first lo cation in memory where the c haracters are to b e stored. READ BTST.W #3, INST A TUS W ait for a c haracter to b e en tered BEQ READ in the k eyb oard buffer DATAIN MO VE.B D A T AIN,(A1) T ransfer the c haracter from D A T AIN in to the memory (this clears SIN to 0). ECHO BTST.W #3,OUTST A TUS W ait for the displa y to b ecome ready . BEQ ECHO MO VE.B (A1),D A T A OUT Mo v e the c haracter just read to the output buffer register (this clears SOUT to 0). CMPI.B #CR,(A1)+ Chec k if the c haracter just read is CR (carriage return). If it is not CR, then BNE READ branc h bac k and read another c haracter. Also, incremen t the p oin ter to store the next c haracter. Figure 3.27. A 68000 program that reads a line of characters and displays it.

  16. Calling program MO VEA.L #NUM1,A2 Put the address NUM1 in A2. MO VE.L N,D1 Put the n um b er of en tries n in D1. BSR LIST ADD Call subroutine LIST ADD. MO VE.L D0,SUM Store the sum in SUM. next instruction . . . Subroutine – LIST ADD SUBQ.L #1,D1 Adjust coun t to n 1. CLR.L D0 LOOP ADD.W (A2)+,D0 Accum ulate sum in D0. DBRA D1,LOOP R TS Figure 3.28. Program of Figure 3.26 written as a 68000 subroutine; parameters passed through registers.

  17. MO VEA.L #LOC,A0 A0 p oin ts to data. MO VE.B (A0)+,D0 Load first b yte in to D0. LSL.B #4,D0 Shift left b y 4 bit p ositions. MO VE.B (A0),D1 Load second b yte in to D1. ANDI.B #$F,D1 Clear high-order 4 bits to zero. OR.B D0,D1 Concatenate the digits. MO VE.B D1,P A CKED Store the result. Figure 3.32. Use of 68000 logic instructions in packing BCD digits.

  18. MO VEA.L #A VEC,A1 Address of first v ector. MO VEA.L #BVEC,A2 Address of second v ector. MO VE N,D0 Num b er of elemen ts. SUBQ #1,D0 Adjust coun t to use DBRA. CLR D1 Use D1 as accum ulator. LOOP MO VE (A1)+,D2 Get elemen t from v ector A. MULS (A2)+,D2 Multiply elemen t from v ector B. ADD D2,D1 Accum ulate pro duct. DBRA D0,LOOP MO VE D1,DOTPR OD Figure 3.33. A 68000 program for computing the dot product of two vectors.

  19. Subroutine INSER TION CMP A.L #0,A0 A0 is RHEAD. BGT HEAD MO VEA.L A1,A0 A1 is RNEWREC. R TS HEAD CMP .L (A0),(A1) Compare ID of new record to head. BGT SEAR CH MO VE.L A0,4(A1) New record b ecomes head. MO VEA.L A1,A0 R TS SEAR CH MO VEA.L A0,A2 A2 is R CURRENT. LOOP MO VEA.L 4(A2),A3 A3 is RNEXT. CMP A.L #0,A3 BEQ T AIL CMP .L (A3),(A1) BL T INSER T MO VEA.L A3,A2 Go to next record. BRA LOOP INSER T MO VE.L A2,4(A1) T AIL MO VE.L A1,4(A2) R TS Figure 3.35. A 68000 subroutine to insert a record in a linked list.

  20. Subroutine DELETION CMP .L (A0),D1 D1 is RIDNUM. BGT SEAR CH MO VEA.L 4(A0),A0 Delete head record. R TS SEAR CH MO VEA.L A0,A2 A2 is R CURRENT. LOOP MO VEA.L 4(A2),A3 A3 is RNEXT. CMP .L (A3),D1 BEQ DELETE MO VEA.L A3,A2 BRA LOOP DELETE MO VE.L 4(A3),D2 D2 is R TEMP . MO VE.L D2,4(A2) R TS Figure 3.36. A 68000 subroutine to delete a record from a linked list.

  21. T able 3.2 68000 addressing modes syn tax Name Assem bler Addressing function Immediate #V alue Op erand = V alue Absolute Short V alue EA = Sign Extended WV alue Absolute Long V alue EA = V alue Register Rn EA = R n that is, Op erand = [R ] n Register Indirect (An) EA = [A ] n Autoincremen t (An)+ EA = [A ]; n Incremen t A n – Auto decremen t (An) Decremen t A ; n EA = [A ] n Indexed basic WV alue(An) EA = WV alue + [A ] n Indexed full BV alue(An,Rk.S) EA = BV alue + [A ] +[R ] n k Relativ e basic WV alue(PC) EA = WV alue + [PC] or Lab el Relativ e full BV alue(PC,Rk.S) EA = BV alue + [PC] + [R ] k or Lab el (Rk) EA = effectiv e address V alue = a n um b er giv en either explicitly or represen ted b y a lab el BV alue = an 8-bit V alue WV alue = a 16-bit V alue A = an address register n R = an address or a data register n S = a size indicator: W for sign-extended 16-bit w ord and L for 32-bit long w ord

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