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Status of H-Cal front-end ASIC

Status of H-Cal front-end ASIC. LAL Orsay J. Fleury, C. de la Taille, G. Martin, L. Raux. Contents. SiPM Readout Prototype DAC for gain Adjustement 1st option : Preamp+CRRC2 shaper 2nd option : Unipolar version: RC6 shaper Backup : FLC_PHY3 Conclusion and perspectives

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Status of H-Cal front-end ASIC

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  1. Status of H-Cal front-end ASIC LAL Orsay J. Fleury, C. de la Taille, G. Martin, L. Raux

  2. Contents • SiPM Readout Prototype • DAC for gain Adjustement • 1st option : Preamp+CRRC2 shaper • 2nd option : Unipolar version: RC6 shaper • Backup : FLC_PHY3 • Conclusion and perspectives • Production schedule • Production cost

  3. SiPM Readout Prototype Chip • 18-Channel Readout Chip Prototype • Technology AMS 0.8 m CMOS • DAC for Si PM Gain adjustment • Preamplifier + Shaper CRRC2 • Unipolar solution RC6 shaper • Track & Hold and multiplexed output ( FLC_PHY3): compatible UK DAQ – Submission in June 2004 – Delivery in September 2004 +HV 100kΩ 100nF SiPM 8-bit DAC input 50Ω ASIC 100nF

  4. DAC Schematic • Adjustement gain DAC • 8-bit DAC excursion 1-5V • Based on ratioed mirror • OTA to avoid early effect (virtual ground)

  5. Channel CRRC2 architecture for SiPM 40kΩ 100MΩ 0.1pF ASIC 2.4pF 8-bit DAC 1-5V 0.2pF 1.2pF 0.4pF 0.6pF 0.8pF 0.3pF in 12kΩ 4kΩ 24pF 10pF 5kΩ 50Ω 12pF 8pF 4pF 2pF 1pF 6pF 100nF Test_pulse 3pF Variable Gain Charge Preamplifier Variable Shaper CR-RC²

  6. Full simulation CRRC2 • Calibration mode • Single photoelectron response • Cf=0.2pF ; τ =12ns • 1 spe = 8.9 mV ; tp=40 ns • Noise : 720 µV rms • Physics mode • MIP (=16pe) response • Cf=0.4pF ; Rc=5k ; τ =120ns • Gain = 12 mV/MIP ; tp=186ns • Noise = 570 µV rms • Cf=0.4pF; Rc=0 ; τ =180ns • Gain =14mV/MIP ; tp=150ns • Noise = 220 µV • Swing voltage: ~2.5V

  7. Unipolar shaper : RC6 architecture 3.5kΩ + 5pF - 7kΩ 11pF 5.5pF 2.8kΩ - + OTA Vref Gm=1uA/V • Unipolar architecture (collaboration with Mephi Group)  RC6 Shaper • Composed with 3 successive RC2 shaper τ=38ns • OTA used for biasing and AC coupling Vout Vin Switch for calibration mode OFF calibration mode/ ON physics mode

  8. Full simulation RC6 • Calibration mode • Single photoelectron response (1pe=160fC) • Gain 9mV/pe tp=30 ns • Noise : 1.4mV rms • Physics mode • MIP (=16pe) response • Gain 17mV/MIP tp=200ns • Noise = 800 µV rms • Dynamic Range [1-125]MIP • Linearity <1% • Swing voltage: ~2.5V 1 MIP response * 125 125 MIP response 1 MIP=16pe response 1 pe response

  9. Backup: FLC_PHY3 10pF 5kΩ 50Ω 200pF FLC_PHY3 • No gain adjustement gain DAC • No Variable shaping No Calibration mode • Measurement in progress • 1000 chips available

  10. Schedule • Prototype Submission inJune 2004 • Prototype Delivery inSeptember 2004 • Test and validation with SiPM inOctober 2004 • Production (1000chips) of the validated version could start inNovember 2004 • Production Delivery expected inJanuary 2005 • Systematic chips test inFebruary 2005 • Chips available for the collaboration byMarch-April 2005

  11. Production cost estimation • Silicon : 1000 dies (area: ~10mm² ) 2 wafers needed: 39 k Euros • Mask : 35 k Euros • Silicon : 4 k Euros • Package : PQFP-100 : 4 k Euros • Total : 43 k Euros • Maybe possibility to share the production with other lab to decrease the production cost

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