S urround G ate M OSFET A n I ntelligent T echnique T o R educe S hort C hannel E ffect

1. Surround Gate MOSFETAn Intelligent Technique To Reduce Short Channel Effect Presenter: Koushik Guha Dept. of Electronics & Communication Engineering National Institute of Technology Silchar, India

2. Outline • Basic MOSFET Operation • Historical Perspective and Motivation • Downscaling of MOSFET • Brief of ShortChannel Effect • Introduction of SOI Technology • DoubleGate Technology • Multi Gate Technology and its features • DMDG-SG………An Innovative Technology • 2D Modeling of DMDG-SG MOSFET • Model Validation with Simulated Results • Conclusion • References

3. TheMetalOxideSemiconductorField-EffectTransistor (MOSFET) In layman terms, MOSFET acts like a switch

4. A Historical Perspective • Moore’s Law • Number of Transistors on an integrated circuit chip doubles every 1.5 years.

5. Motivation • Silicon-only planar transistors are fast approaching their scaling limit. • Short channel effects limiting scaling into sub nanometer regime. • Oxide thickness cannot be scaled down further, problems of tunneling. • Need to keep Silicon technology as the base technology while innovating future devices; cost is an important factor. • Performance and power dissipation need to be improved. • Smaller is faster !!

6. Why Scale? Decrease the gate length Increase speed Increase Packing density Decrease Costs?

7. MOSFET Scaling Trends

8. Scaling limits of BULK MOSFET • Limit for supply voltage (<0.6V) • Limit for further scaling of tox (<2nm) • Minimum channel length Lg= 50nm • Discrete dopant fluctuations • Dramatic short-channels effects (SCE)

9. How can we follow Moore’s law? By moving to Multiple Gate MOSFETs MG might be the unique viable alternative to build nano MOSFETs when Lg<50nm Because: - Better control of the channel from the gates - Reduced short-channel effects - Better Ion/Ioff - Improved sub-threshold slope (60mV/decade) - No discrete dopant fluctuations

11. Short Channel Effect

18. Short Channel Effect in bulk-MOS Short channel effect in bulk-CMOS devices is a major barrier to scaling

19. Drain Induced Barrier Lowering

24. SOI – The technology of the future • Highlights • Reduced junction capacitance. • Absence of latch up. • Ease in scaling (buried oxide need not be scaled). • Compatible with conventional Silicon processing • Sometimes requires fewer steps to fabricate. • Reduced leakage. • Improvement in the soft error rate. Welcome to the world of Silicon On Insulator • Drawbacks • Drain Current Overshoot. • Kink effect • Thickness control (fully depleted operation). • Surface states.

25. SOI Technology Silicon-on-Insulator (SOI) Approach • Silicon channel layer grown on a layer of oxide. • Absence of junction capacitance makes this an attractive option. • Low leakage currents and compatible fabrication technology.

26. Silicon-on-Insulator (SOI) Approach • Silicon channel layer grown on a layer of oxide. • Absence of junction capacitance makes this an attractive option. • Low leakage currents and compatible fabrication technology.

27. Classification of SOI MOSFETs Partially depleted SOI MOSFET Conventional MOSFET Fully depleted SOI MOSFET • Silicon film thickness greater than bulk depletion width for a partially-depleted MOSFET and less than the gate depletion width for a fully-depleted MOSFET. • Partially depleted MOSFETs often plagued by KINK effects, fully depleted devices virtually free from such effects. • Partially depleted devices can be faster than fully depleted devices under certain operating conditions.

28. Why Several Gates?

29. Advantages of Double Gate Devices • Short channel effect control • Better scalability • Lower sub threshold current • Higher On Current • Near-Ideal Sub threshold slope • Lower Gate Leakage • Elimination of Vt variation due to Random dopant fluctuation DG devices are very promising for circuit design in sub-50nm technology

30. Double gates electrically shield the channel To reduce SCE’s, aggressively reduce Si layer thickness BOX BOX Double-Gate Single-Gate SOI Field Lines for Single-Gate & Double-Gate SOI MOSFETs

31. Double Gate Device • Single Gate to Double Gates • Better short-channel effect control • More Scalable

32. Why Multi-Gate SOI MOSFETs ? • Higher current drive  better performance • Prophesized to show higher tolerance to scaling. • Better integration feasibility, raised source-drain structure, ease in integration. • Larger number of parameters to tailor device performance

33. Multi-Gate SOI MOSFETs (3-D Views) TriGate Double Gate/FinFET QuadGate -Gate

34. Gate All Around MOSFET- 3D View

35. Cylindrical Dual Material Surround Gate MOSFET(CDMSG-MOS) Cross section view of CDSG Structure of n channel FD-DMSG MOSFET 3D structure of CDSG

36. DMDG-SG MOSFET- A Potential competitor Vertical DMSG structure Cross section view through channel Dual-material gate (DMG) structure employs “gate-material engineering” instead of “doping engineering” with different work functions to introduce a potential step in the channel. This leads to a suppression of SCEs and an enhanced source side electric field resulting in increased carrier transport efficiency in the channel region.

37. 2D Surface Potential Modeling of Our Structure In conventional Surrounding Gate MOSFET (C-SG) MOSFET, the gate is made of only one material, but in the Double material isolated Surround Gate (DMISG) MOSFET structure, we have two gates with different work functions and doping density under them along with a gap in the considered structure. After solving 2D Poisson equation at different surfaces and satisfying boundary conditions at interfaces we obtained mathematical function of Electric Field and Electrostatic Potential at different interfaces and along the channel region. Simulated structure of DMSIG

38. Model Validation with Simulation Results Figure:1 Fig. 1 shows the variation of the surface electrostatic potential for the typical device parameters with gate voltages of M1 and M2 fixed at 0.0 V. The drain voltage is varied from 0.0 to 1.5 V. As can be observed from the Fig. 2 that the model is able predict the surface potential in agreement with the 2D simulation results for the different drain voltages. It is observed that the variation in the drain voltage is not changing the minimum potential under the gate M1. It means that the gate M1 is “screened” from the variations in the drain voltage and all the drain voltage is dropped under M2 only. This reduces the DIBL and threshold voltage roll off effects.

39. Figure:2 Figure.2 shows the Electric Field variation along the channel. It is observed that field remains almost constant under Metal 1 and peak field occurs at the gap region.

40. Figure:3 Figure 3 shows the electrostatic potential comparison of simulation results for different L1/L2 ratios, VGS1=0.1 V, VGS2=0.8 V and VDS=0.5 V. It is observed that when the L1 is larger than the L2, then potential under M1 is less affected due to the VDS voltage whereas when the L1 is lower than the L2, then the drain voltage influences the potential under M1. In the case when L1=L2 then this looks to be optimum case and the potential under M1 is also not much affected by VDS, reducing the DIBL effect.

41. Conclusions • DMDG-SG devices are promising for low power and high frequency circuit design • Better scalability • DMDG-SG technologies provide unique opportunities for designers • Proper use of different types of devices can maximize the advantage of the DG technologies. • A new physics based surface potential model for the double material double gate surrounding gate (DMDG-SG) SOI MOSFET has been successfully derived and validated with the TCAD Device simulation results. • It has been found that our model is in well agreement with different drain biasing voltages and other device parameters. • The usefulness of this device against the SCEs and HCEs has also been demonstrated through the simulations results. Surround Gate technologies with proper design parameters are attractive for circuit design in nanometer era

42. References • A. Breed and K.P. Roenker, “Dual-gate (FinFET) and TriGate MOSFETs: Simulation and design,” Proceedings of the International Semiconductor Device Research Symposium (ISDRS-2003), pp. 150-151, December 2003. • J-T. Park and J-P Colinge, “Multiple-Gate SOI MOSFETs: Device Design Guidelines,” IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12, Dec. 2002. • Aniket Breed and Kenneth P. Roenker, “A Small-signal, RF Simulation Study of Multiple-gate MOSFET Devices,” IEEE Topical Meeting on Silicon Monolithic ICs in RF Systems, Atlanta, GA, Sept. 2004. • Biswajit Ray , Santanu Mahapatra “A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor”, 21st International Conference on VLSI Design, 1063-9667/08, DOI 10.1109/VLSI.2008.52, page 447-452. • Cong Li, Yiqi Zhuang, Ru Han “Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension”, Microelectronics Journal

43. Thank You