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Microprocessor-based Systems Course 3

Microprocessor-based Systems Course 3. A (simple) computer structure. Instruction format. Operation code. - Without explicit operands. - With one operand. Operation code. Operand1 - Address. Operation code. Operand1 - Address. Operand2 - Address/Data. - With 2 operands.

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Microprocessor-based Systems Course 3

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  1. Microprocessor-based SystemsCourse 3 A (simple) computer structure

  2. Instruction format Operation code - Without explicit operands - With one operand Operation code Operand1 - Address Operation code Operand1 - Address Operand2 - Address/Data - With 2 operands Operand1 - Address Operand2 - Address/Data Result - Address Operation code - With 2 operands and a result

  3. Addressing modes • How the operand is determined • Immediate addressing – for constants • MOV AX, 1234h • Direct addressing – for simple variables • SUB BX, [100h] • Indexed addressing – for vectors • ADD [SI+500h], AX • Based addressing – for records • AND DX, [BX+200h] • Mixed (based and indexed) – for complex data structures • OR CX, [SI+BX+100h]

  4. 0 0 a b c x x x The instruction set of a simple computer Op. code: 0 0 0 1 1 0 1 1 7 6 5 0 7 6 5 4 3 2 1 0 Op. code Address field 0 0 0 0 0 1 . . . 1 1 1

  5. Data display The general scheme of a simple computer Address display STOP START Clock gen. Sel_Op Sel_I/D Ld_IR CLK IR – instruction reg. M U X INIT M Phase gen. OC OC/Addr WrM UAL 1 0 Decoder and comand block Man/Auto MUX LdPC Program counter IncPC micocomands SHR A Ld_A MUX Man/Auto SHL RstA Front panel Addr. switches Data switches

  6. Decomposition of instructions into phases INIT I1 Sel_I/D=0 Ld_IR I2 IncPC E1 E1 STOP SHR SHL JMP MEM NOP CLA CPL ADD SKIPO SKIPN Sel_I/D=1 Sel_op=0 1 1 Sel_I/D=1 Sel_op=1 LdPC RstA A7 A0 IncPC IncPC 0 0 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 Sel_I/D=1 LdA SHR SHL STOP WrM LdA

  7. Sel_I/D = E1  (ADD + MEM) I1 I2 E1 E2 DEC ADD CLK Modulo 4 counter CG Sel_I/D MEM I1 I2 E1 E2 MEM NOP CCB INIT E1 Sel_I/D STOP microcommands Phase generator (PG), Instruction decoder (ID) and Command and control block (CCB) RI 7 6 5 4 3 2 1 0 2 3 DEC 11 MEM JMP DEC ADD NOP Stop a. Phase generator b. Instruction decoder b. Implementation of the Sel_I/D cmd. a. The contro and command block

  8. Sequential execution of instructions (Scalar architecture) • Execution phases of an instruction: • Instruction fetch (IF) • Instruction decode (ID) • Execution (Ex) • Memory operation (Mem) • Write back (Wr) • CPI = 5 IF ID Ex Me Wr IF ID Ex Me Wr IF ID Ex Me Wr Instr. 1 Instr. 2 Instr. 3

  9. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 IF ID Ex Mem Wr IF ID Ex Mem Wr instruction i1 instruction i2 Sequential execution CPI = 5 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 i1 IF ID Ex Mem Wr IF ID Ex Mem Wr i2 i3 IF ID Ex Mem Wr i4 IF ID Ex Mem Wr i6 IF ID Ex Mem Wr Parallel execution CPI=1 (ideal case) Comparison between sequential and pipeline execution Parallel instruction execution on a pipeline architecture (assembly line)

  10. A Reg. block. Data mem. Instr. mem. Reg. block M IR R addr. instr. addr B Di D I ex me wr P C D e c me wr +4 wr C1 C2 C3 IF ID Ex Mem Wr A CPU with a pipeline structure Example of a pipeline architecture

  11. IF ID Ex Mem Wr MOV AX, 5 IF ID Ex Wr ADD BX, AX IF ID Ex Wr SUB CX, 5 IF ID Ex Mem MOV DX, CX Hazard cases in pipeline architecture • Data hazard • Data dependency between consecutive instructions • Solutions: • Idle states, multiple registers, instruction reordering

  12. JE et1 IF ID Ex ADD AX, BX IF ID Ex Wr SUB CX, DX IF ID Ex Wr ............... et1: MOV SI, 1234h IF ID Ex Mem Wr Hazard cases in pipeline architecture • Control hazard • Caused by jump/branch instructions • Solutions: branch prediction, memorize previous jumps

  13. IF ID Ex Mem Wr IF ID Ex Wr Hazard cases in pipeline architecture • Structural hazard • Two different phases of consecutive instructions require the same structural unit (e.g. ALU, memory, etc.) • Solutions: Idle states, instruction reordering, multiple structural units (e.g. multiple execution units, ALUs, data memory and instruction memory)

  14. Superscalar and superpipeline architectures T1 T2 T3 T4 T5 T6 instr. i IF ID Ex Mem Wr a. Superscalar architecture CPI=1/2 instr. i+1 IF ID Ex Mem Wr instr. i+2 IF ID Ex Mem Wr instr. i+3 IF ID Ex Mem Wr T1 T2 T3 T4 T5 T6 instr. i IF ID Ex Mem Wr b. Superpipeline architecture CPI=1/2 instr. i+1 IF ID Ex Mem Wr instr. i+2 IF ID Ex Mem Wr instr. i+3 IF ID Ex Mem Wr Comparison between superscalar and superpipeline architectures

  15. Scheduling instruction execution • Objective: reordering instruction execution in order to avoid hazard situations and increase performance • Static scheduling: • Reordering in the compilation phase • Instructions are grouped in Very Long Instruction Words • VLIW – Very Long Instruction Word • Dynamic scheduling: • Reordering during the execution of a program • Techniques: data flow analysis, dependency trees, branch predictions

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