Component Identification

1. Component Identification By: Ankur Agarwal Under the Guidance of : Ravi Shankar

2. Presentation Flow • Process of Component Identification • Component Specification • Concurrency Modeling • Component Equivalency • Component Modeling in MLD • Example of NOC Components • NOC Component Specification • NOC Concurrency Modeling • NOC Component Equivalency • Component Modeling in MLD

3. Why Components • Backbone of OPP Project • Reusability • Object Oriented Components • Component Abstraction at different levels of abstraction

4. Process of Component Design Verification Literature Survey Mapping to Practical Blocks Component Discovery Generalization Component Characterization

5. Component Specification • Methods • Functionality of each component • Attributes • Inputs and Outputs of a component • Concurrency • Synchronizing Interfaces • Cost • Performance parameters • Parameters • Customization

6. Concurrency Modeling High Level System Specification Identify Concurrent Processes Model Process Interactions Analyze System for Deadlock/Livelock/ Starvation Re-Do Component Specification

7. Component Equivalency • Concurrency Component • Match sub-system specification • Finalize component list • Compare sub-System functionality

8. State N N O1 State oi1 I1 VC1 VC2 S State State O2 S oi2 I2 VC1 VC2 E O3 State State E I3 oi3 VC1 VC2 W O4 State State W oi4 I4 VC1 VC2 Switch Allocator Virtual Channel Allocator NI State Router NI NI State I0 VC1 VC2 NOC Example Virtual Channel Router

9. Interconnection Network Virtual-Channel Router Input Port Header Processor Virtual Channel Flit Buffers Routing Block Output Port FIFO Buffer Virtual Channel Allocator Switch Allocator Crossbar Switch Network Interface Input Port Output Port Scheduler Packet Builder Flit Builder Depacketizer Flit Striper Credit Controller Old Component List

10. COMPONENT DESCRIPTION • Input Port • Extracts Header Information from Data packets & Stores Data Packets • Router • Determines Path for Data Packets • Allocator • Selects VC on Output Port • Switch • Interconnects the Input Port to the Output Port • Output Port • Contains Queues for Holding Data packets • Link • Interconnects Neighboring Nodes

11. Example of NOC Components

12. NOC Concurrency Model • Demo

13. N S Bi Bo N S Bi Bo N S Bi Bo P/C P/C P/C Bi Bo Bi Bo Bi Bo N S Bi Bo N S Bi Bo N S Bi Bo P/C P/C P/C Bi Bo Bi Bo Bi Bo N S Bi Bo N S Bi Bo N S Bi Bo P/C P/C P/C DESIGNED NOC COMPONENT P: PRODUCER Bi: I/P BUFFER Bo: O/P BUFFER L: LINK N: NODE S: SCHEDULER C: CONSUMER

14. COMPONENT EQUIVALENCY • Buffer • Queue & Virtual Channel • Scheduler • Scheduler & Allocator • Node • Switch & Router • Producer/Consumer • HW/SW Resource

15. Extracting Performance Parameters for Components

16. Extracting Performance Parameters for Components

17. Extracting Performance Parameters for Components

18. MLD IMPLEMENTATION OF BUFFER COMPONENT Internal Specifics of Buffer Buffer Interface with Other Components

19. MLD IMPLEMENTATION OF SCHEDULER COMPONENT Internal Specifics of Scheduler Scheduler Interface with Other Components

20. MLD IMPLEMENTATION OF PRODUCER COMPONENT Internal Specifics of Producer

21. MLD IMPLEMENTATION OF NODE COMPONENT Internal Specifics of Node

22. INTEGRATION OF NOC COMPONENTS

23. NOC SUB-SYSTEM: 4×4 MESH

24. SEQUENCE OF OPERATION • 1st Clock Cycle • Storing the Data Packets into the Buffer • 2nd clock Cycle • Requesting Data Output to Scheduler • 3rd Clock Cycle • Grant Signal from Scheduler • 4th Clock Cycle • Forwarding Data Packet to Node • 5th Clock Cycle • Confirming Output Buffer Availability • 6th Clock Cycle • Forwarding Data Packet to Next Node

25. SIMULATION RESULT FOR LATENCY Latency for Low-Priority Data Packets % Forward Packets Latency In Clock Cycles Latency for Hi-Priority Data Packets % Forward Packets Latency In Clock Cycles